公开(公告)号：US07790523B2

公开(公告)日：2010-09-07

申请号：US11861113

申请日：2007-09-25

Applicant: Young-Wook Lee ,  Woo-Geun Lee ,  Jung-In Park ,  Youn-Hee Cha

Inventor： Young-Wook Lee ,  Woo-Geun Lee ,  Jung-In Park ,  Youn-Hee Cha

IPC: H01L21/00 ,  H01L21/84

CPC classification number: H01L29/41733 ,  H01L27/124 ,  H01L27/1288

Abstract: A mask that is capable of forming a thin-film transistor (TFT) with improved electrical characteristics is presented. The mask includes a drain mask pattern, a source mask pattern and a light-adjusting pattern. The drain mask pattern blocks light for forming a drain electrode. The source mask pattern blocks light for forming a source electrode and faces the drain mask pattern. A distance between the drain and source mask patterns is no more than the resolution of an exposing device. The light-adjusting pattern is formed between end portions of the source mask pattern and the drain mask pattern to block at least some light from entering a space between the source and drain mask patterns.

Abstract translation: 提出了能够形成具有改善的电特性的薄膜晶体管（TFT）的掩模。 掩模包括漏极掩模图案，源掩模图案和调光图案。 漏极掩模图案阻挡用于形成漏电极的光。 源极掩模图案阻挡用于形成源极的光，并面向漏极掩模图案。 漏极和源极掩模图案之间的距离不大于曝光装置的分辨率。 光源调制图案形成在源掩模图案和漏极掩模图案的端部之间，以阻挡至少一些光进入源极和漏极掩模图案之间的空间。

公开(公告)号：US20090302316A1

公开(公告)日：2009-12-10

申请号：US12464920

申请日：2009-05-13

Applicant: Woo-Geun LEE ,  Jae-Hyoung YOUN ,  Ki-Won KIM ,  Young-Wook LEE ,  Jong-In KIM

Inventor： Woo-Geun LEE ,  Jae-Hyoung YOUN ,  Ki-Won KIM ,  Young-Wook LEE ,  Jong-In KIM

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L29/78696

Abstract: A thin film transistor array panel includes a substrate, a gate line formed on the substrate and including a gate electrode, a gate insulating layer formed on the gate line, a semiconductor formed on the gate insulating layer and including a channel of a thin film transistor, a data line formed on the semiconductor and including a source electrode and a drain electrode formed on the semiconductor and opposite to the source electrode with respect to the channel of the thin film transistor, wherein the channel of the thin film transistor covers both side surfaces of the gate electrode.

Abstract translation: 薄膜晶体管阵列面板包括基板，形成在基板上的栅极线，包括栅极电极，形成在栅极线上的栅极绝缘层，形成在栅极绝缘层上并包括薄膜晶体管的沟道的半导体 ，形成在半导体上的数据线，包括相对于薄膜晶体管的沟道形成在半导体上并与源电极相对的源电极和漏电极，其中薄膜晶体管的沟道覆盖两个侧表面 的栅电极。

公开(公告)号：US07570464B2

公开(公告)日：2009-08-04

申请号：US10498099

申请日：2002-10-11

Applicant: Young-Hoan Jun ,  Dong-Hee Shin ,  Gyoo-Jong Bae ,  Woo Geun Lee

Inventor： Young-Hoan Jun ,  Dong-Hee Shin ,  Gyoo-Jong Bae ,  Woo Geun Lee

IPC: H02H7/00

CPC classification number: F04B49/065 ,  F04B35/045 ,  F04B49/02 ,  F04B2201/0206 ,  F04B2203/0401 ,  F04B2203/0402 ,  H02P25/032

Abstract: In an overload protective apparatus of a compressor and its method capable of preventing damage of a compressor due to overload by removing an overload protector and using an operation control device operating the compressor, the overload protective apparatus includes a reference current setting unit for presetting a reference current value for operating the compressor normally; a microcomputer for generating a power cutoff signal when the detected current value is greater than the reference current value and generating a power supply signal when the detected current value is smaller than the reference current value; and a power supply unit for cutting off power applied to the compressor on the basis of the power cutoff signal or applying power to the compressor on the basis of the power supply signal.

Abstract translation: 在压缩机的过载保护装置及其方法中，能够通过去除过载保护器和使用操作压缩机的操作控制装置来防止压缩机由于过载而造成的损坏，该过载保护装置包括：参考电流设定单元，用于预设参考 正常运行压缩机的当前值; 微型计算机，当所检测的电流值大于所述基准电流值时，产生电力切断信号，并且当所检测的电流值小于所述基准电流值时产生电源信号; 以及电源单元，用于根据电力切断信号切断施加到压缩机的电力，或者根据电源信号对压缩机施加电力。

公开(公告)号：US07425476B2

公开(公告)日：2008-09-16

申请号：US11242696

申请日：2005-10-04

Applicant: Woo-Geun Lee ,  Hye-Young Ryu ,  Sang-Gab Kim ,  Jang-Soo Kim

Inventor： Woo-Geun Lee ,  Hye-Young Ryu ,  Sang-Gab Kim ,  Jang-Soo Kim

IPC: H01L21/00

CPC classification number: H01L27/1288 ,  H01L21/32134 ,  H01L21/76838 ,  H01L27/1214 ,  H01L29/66765

Abstract: A method of manufacturing a thin film transistor array panel includes forming a gate line including a gate electrode, forming a gate insulating layer on the gate line, forming a semiconductor stripe on the gate insulating layer; forming ohmic contacts on the semiconductor stripe, forming a data line including a source electrode and a drain electrode on the ohmic contacts, depositing a passivation layer on the data line and the drain electrode, and forming a pixel electrode connected to the drain electrode. The formation of the data line and the drain electrode, the ohmic contacts, and the semiconductor stripe includes depositing an intrinsic silicon layer, an extrinsic silicon layer, and a conductor layer on the gate insulating layer, forming a photoresist including a second portion corresponding to a channel area between the source electrode and the drain electrode, and a first portion corresponding to a wire area on the data line and the drain electrode, wherein the first portion is thicker than the second portion, etching the conductor layer corresponding to a remaining area except for the wire and the channel area using the photoresist as an etch mask, removing the second portion to expose the conductor layer on the channel areas, etching the intrinsic silicon layer and the extrinsic silicon layer on the remaining area, etching the conductor layer and the extrinsic silicon layer on the channel areas, and removing the first portion.

Abstract translation: 制造薄膜晶体管阵列面板的方法包括：形成包括栅电极的栅极线，在栅极线上形成栅绝缘层，在栅绝缘层上形成半导体条; 在半导体条上形成欧姆接触，在欧姆接触上形成包括源电极和漏电极的数据线，在数据线和漏电极上沉积钝化层，并形成连接到漏电极的像素电极。 数据线和漏电极，欧姆接触和半导体条纹的形成包括在栅绝缘层上沉积本征硅层，非本征硅层和导体层，形成光致抗蚀剂，其包括对应于 源极电极和漏极电极之间的沟道区域，以及对应于数据线和漏极电极的导线区域的第一部分，其中第一部分比第二部分厚，蚀刻对应于剩余区域的导体层 除了使用光致抗蚀剂作为蚀刻掩模的导线和沟道区域之外，去除第二部分以暴露沟道区域上的导体层，蚀刻剩余区域上的本征硅层和非本征硅层，蚀刻导体层和 在通道区域上的非本征硅层，以及去除第一部分。

公开(公告)号：US20060073645A1

公开(公告)日：2006-04-06

申请号：US11242696

申请日：2005-10-04

Applicant: Woo-Geun Lee ,  Hye-Young Ryu ,  Sang-Gab Kim ,  Jang-Soo Kim

Inventor： Woo-Geun Lee ,  Hye-Young Ryu ,  Sang-Gab Kim ,  Jang-Soo Kim

IPC: H01L21/84

CPC classification number: H01L27/1288 ,  H01L21/32134 ,  H01L21/76838 ,  H01L27/1214 ,  H01L29/66765

Abstract: A method of manufacturing a thin film transistor array panel includes forming a gate line including a gate electrode, forming a gate insulating layer on the gate line, forming a semiconductor stripe on the gate insulating layer; forming ohmic contacts on the semiconductor stripe, forming a data line including a source electrode and a drain electrode on the ohmic contacts, depositing a passivation layer on the data line and the drain electrode, and forming a pixel electrode connected to the drain electrode. The formation of the data line and the drain electrode, the ohmic contacts, and the semiconductor stripe includes depositing an intrinsic silicon layer, an extrinsic silicon layer, and a conductor layer on the gate insulating layer, forming a photoresist including a second portion corresponding to a channel area between the source electrode and the drain electrode, and a first portion corresponding to a wire area on the data line and the drain electrode, wherein the first portion is thicker than the second portion, etching the conductor layer corresponding to a remaining area except for the wire and the channel area using the photoresist as an etch mask, removing the second portion to expose the conductor layer on the channel areas, etching the intrinsic silicon layer and the extrinsic silicon layer on the remaining area, etching the conductor layer and the extrinsic silicon layer on the channel areas, and removing the first portion.

Abstract translation: 制造薄膜晶体管阵列面板的方法包括：形成包括栅电极的栅极线，在栅极线上形成栅绝缘层，在栅绝缘层上形成半导体条; 在半导体条上形成欧姆接触，在欧姆接触上形成包括源电极和漏电极的数据线，在数据线和漏电极上沉积钝化层，并形成连接到漏电极的像素电极。 数据线和漏电极，欧姆接触和半导体条纹的形成包括在栅绝缘层上沉积本征硅层，非本征硅层和导体层，形成光致抗蚀剂，其包括对应于 源极电极和漏极电极之间的沟道区域，以及对应于数据线和漏极电极的导线区域的第一部分，其中第一部分比第二部分厚，蚀刻对应于剩余区域的导体层 除了使用光致抗蚀剂作为蚀刻掩模的导线和沟道区域之外，去除第二部分以暴露沟道区域上的导体层，蚀刻剩余区域上的本征硅层和非本征硅层，蚀刻导体层和 在通道区域上的非本征硅层，以及去除第一部分。

公开(公告)号：US08836877B2

公开(公告)日：2014-09-16

申请号：US13277114

申请日：2011-10-19

Applicant: Seung-Ha Choi ,  Kyoung-Jae Chung ,  Woo-Geun Lee

Inventor： Seung-Ha Choi ,  Kyoung-Jae Chung ,  Woo-Geun Lee

IPC: G02F1/136 ,  H01L29/786 ,  G02F1/1362 ,  H01L29/66 ,  H01L29/49 ,  H01L27/12

CPC classification number: H01L21/3086 ,  G02F1/136227 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/7869

Abstract: Provided are a display substrate, a display device, and a method of manufacturing the display substrate. The display substrate includes: a substrate in which a pixel region is defined; a gate electrode and a gate pad are formed on the substrate; a gate insulating layer formed on the gate electrode and the gate pad; a buffer layer pattern overlaps the gate electrode and is formed on the gate insulating layer; an insulating film pattern formed on the buffer layer pattern; an oxide semiconductor pattern formed on the insulating film pattern; a source electrode formed on the oxide semiconductor pattern; and a drain electrode formed on the oxide semiconductor pattern and is separated from the source electrode.

Abstract translation: 提供了显示基板，显示装置和制造显示基板的方法。 显示基板包括：限定像素区域的基板; 在基板上形成栅电极和栅极焊盘; 形成在栅极电极和栅极焊盘上的栅极绝缘层; 缓冲层图案与栅电极重叠并形成在栅极绝缘层上; 形成在缓冲层图案上的绝缘膜图案; 形成在所述绝缘膜图案上的氧化物半导体图案; 形成在所述氧化物半导体图案上的源电极; 以及形成在氧化物半导体图案上并与源电极分离的漏电极。

公开(公告)号：US08772897B2

公开(公告)日：2014-07-08

申请号：US13049783

申请日：2011-03-16

Applicant: Ki-Won Kim ,  Kap-Soo Yoon ,  Woo-Geun Lee ,  Yeong-Keun Kwon ,  Hye-Young Ryu ,  Jin-Won Lee ,  Hyun-Jung Lee

Inventor： Ki-Won Kim ,  Kap-Soo Yoon ,  Woo-Geun Lee ,  Yeong-Keun Kwon ,  Hye-Young Ryu ,  Jin-Won Lee ,  Hyun-Jung Lee

IPC: H01L27/146

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/78645 ,  H01L29/78648

Abstract: A thin-film transistor includes a semiconductor pattern, a first gate electrode, a source electrode, a drain electrode and a second gate electrode. The semiconductor pattern is formed on a substrate. A first conductive layer has a pattern that includes the first gate electrode which is electrically insulated from the semiconductor pattern. A second conductive layer has a pattern that includes a source electrode electrically connected to the semiconductor pattern, a drain electrode spaced apart from the source electrode, and a second gate electrode electrically connected to the first gate electrode. The second gate electrode is electrically insulated from the semiconductor pattern, the source electrode and the drain electrode.

Abstract translation: 薄膜晶体管包括半导体图案，第一栅电极，源电极，漏电极和第二栅电极。 半导体图案形成在基板上。 第一导电层具有包括与半导体图案电绝缘的第一栅电极的图案。 第二导电层具有图案，其包括电连接到半导体图案的源电极，与源电极间隔开的漏电极和与第一栅电极电连接的第二栅电极。 第二栅电极与半导体图案，源电极和漏电极电绝缘。

公开(公告)号：US08723179B2

公开(公告)日：2014-05-13

申请号：US12957743

申请日：2010-12-01

Applicant: Pil-Sang Yun ,  Ki-Won Kim ,  Hye-Young Ryu ,  Woo-Geun Lee ,  Seung-Ha Choi ,  Jae-Hyoung Youn ,  Kyoung-Jae Chung ,  Young-Wook Lee ,  Je-Hun Lee ,  Kap-Soo Yoon ,  Do-Hyun Kim ,  Dong-Ju Yang ,  Young-Joo Choi

Inventor： Pil-Sang Yun ,  Ki-Won Kim ,  Hye-Young Ryu ,  Woo-Geun Lee ,  Seung-Ha Choi ,  Jae-Hyoung Youn ,  Kyoung-Jae Chung ,  Young-Wook Lee ,  Je-Hun Lee ,  Kap-Soo Yoon ,  Do-Hyun Kim ,  Dong-Ju Yang ,  Young-Joo Choi

IPC: H01L29/04 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20

CPC classification number: H01L29/41733 ,  H01L21/44 ,  H01L21/441 ,  H01L21/465 ,  H01L21/475 ,  H01L21/47573 ,  H01L21/47635 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.

Abstract translation: 薄膜晶体管面板包括绝缘基板，设置在绝缘基板上的栅极绝缘层，设置在栅极绝缘层上的氧化物半导体层，设置在氧化物半导体层上的蚀刻停止器，以及设置在源极电极和漏极上的 在蚀刻停止器上。

公开(公告)号：US08598583B2

公开(公告)日：2013-12-03

申请号：US13092882

申请日：2011-04-22

Applicant: Hye-Young Ryu ,  Jin-Won Lee ,  Woo-Geun Lee ,  Hee-Jun Byeon ,  Xun Zhu

Inventor： Hye-Young Ryu ,  Jin-Won Lee ,  Woo-Geun Lee ,  Hee-Jun Byeon ,  Xun Zhu

IPC: H01L29/786

CPC classification number: H01L27/1288 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/3272 ,  H01L51/5253 ,  H01L2227/323

Abstract: A thin film transistor panel includes a substrate, a light blocking layer on the substrate, a first protective film on the light blocking layer, a first electrode and a second electrode on the first protective film, an oxide semiconductor layer on a portion of the first protective film exposed between the first electrode and the second electrode, an insulating layer, a third electrode overlapping with the oxide semiconductor layer and on the insulating layer, and a fourth electrode on the insulating layer. The light blocking layer includes first sidewalls, and the first protective film includes second sidewalls. The first and the second sidewalls are disposed along substantially the same line.

公开(公告)号：US08461585B2

公开(公告)日：2013-06-11

申请号：US13111027

申请日：2011-05-19

Applicant: Young-Joo Choi ,  Woo-Geun Lee ,  Do-Hyun Kim

Inventor： Young-Joo Choi ,  Woo-Geun Lee ,  Do-Hyun Kim

IPC: H01L29/10 ,  H01L29/12

CPC classification number: H01L27/1225

Abstract: A display substrate includes; a gate pattern including a gate electrode disposed on a substrate, a gate insulation layer disposed on the substrate and the gate pattern, an insulation pattern including; a first thickness part disposed on a first area of the gate insulation layer overlapping the gate electrode and a second thickness part disposed on a second area of the gate insulation layer adjacent to the first area, an oxide semiconductor pattern disposed on the first thickness part of the first area, an etch stopper disposed on the oxide semiconductor pattern, a source pattern including a source electrode and a drain electrode which contact the oxide semiconductor pattern, and a pixel electrode which contacts the drain electrode.

Abstract translation: 显示基板包括： 栅极图案，包括设置在基板上的栅极电极，设置在基板上的栅极绝缘层和栅极图案，绝缘图案，包括： 设置在与栅电极重叠的栅极绝缘层的第一区域上的第一厚度部分和设置在与第一区域相邻的栅极绝缘层的第二区域上的第二厚度部分，设置在栅极绝缘层的第一厚度部分上的氧化物半导体图案 第一区域，设置在氧化物半导体图案上的蚀刻停止件，包括与氧化物半导体图案接触的源电极和漏电极的源图案以及与漏电极接触的像素电极。