公开(公告)号：US20120297351A1

公开(公告)日：2012-11-22

申请号：US13371487

申请日：2012-02-13

申请人： Jaeheon SHIN ,  Woo-Seok Cheong ,  Chi-Sun Hwang ,  Sung Mook Chung

发明人： Jaeheon SHIN ,  Woo-Seok Cheong ,  Chi-Sun Hwang ,  Sung Mook Chung

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： Methods of modeling a transistor are provided. The method includes the steps of (a) extracting reference mobility values of a channel layer of a transistor including a gate electrode, a source region and a drain region using a reference gate voltage, a reference drain current and a reference drain voltage, (b) fitting a mobility function including model parameters on the reference mobility values to extract the model parameters, and (c) putting the extracted model parameters into a drain current modeling function to calculate a drain current flowing through the channel layer between the drain region and the source region under a bias condition defined by an arbitrary gate voltage applied to the gate electrode and an arbitrary drain voltage applied to the drain region. Related apparatuses are also provided.

摘要翻译： 提供了对晶体管进行建模的方法。 该方法包括以下步骤：（a）使用参考栅极电压，参考漏极电流和参考漏极电压提取包括栅电极，源区和漏区的晶体管的沟道层的参考迁移率值，（b ）将包括模型参数的移动性函数拟合在参考迁移率值上以提取模型参数，以及（c）将所提取的模型参数放入漏极电流建模函数中以计算流过漏极区域和漏极区域之间的沟道层的漏极电流 源极区域由施加到栅极电极的任意栅极电压和施加到漏极区域的任意漏极电压限定的偏置状态。 还提供了相关装置。

公开(公告)号：US20120103259A1

公开(公告)日：2012-05-03

申请号：US13182955

申请日：2011-07-14

申请人： Woo-Seok CHEONG ,  Yeong-Shin Kim

发明人： Woo-Seok CHEONG ,  Yeong-Shin Kim

IPC分类号： C23C16/50

CPC分类号： C23C14/562 ,  C23C14/3435

摘要： Provided is a thin film depositing apparatus. The thin film depositing apparatus includes: a process chamber including at least one sputter gun inducing a first plasma on a film or a flat plate; a loading unit provided at one side of the process chamber and including first and second loading chambers loading the film or the flat plate into the process chamber; and an unloading unit provided at the other side of the process chamber facing the loading unit and including first and second loading chambers including first and second unloading chambers unloading the film or the flat plate from the process chamber, wherein the first loading chamber is connected to the first unloading chamber or the second loading chamber is connected to the second unloading chamber at both sides of the process chamber.

摘要翻译： 提供了一种薄膜沉积设备。 薄膜沉积设备包括：处理室，包括在薄膜或平板上引入第一等离子体的至少一个溅射枪; 设置在处理室的一侧并且包括将膜或平板装载到处理室中的第一和第二装载室的装载单元; 以及卸载单元，设置在所述处理室的面向所述装载单元的另一侧，并且包括第一和第二装载室，所述第一和第二装载室包括从所述处理室卸载所述膜或所述平板的第一和第二卸载室，其中所述第一装载室连接到 第一卸载室或第二装载室在处理室的两侧连接到第二卸载室。

公开(公告)号：US08071434B2

公开(公告)日：2011-12-06

申请号：US12560702

申请日：2009-09-16

申请人： Woo Seok Cheong ,  Sung Mook Chung ,  Min Ki Ryu ,  Chi Sun Hwang ,  Hye Yong Chu

发明人： Woo Seok Cheong ,  Sung Mook Chung ,  Min Ki Ryu ,  Chi Sun Hwang ,  Hye Yong Chu

IPC分类号： H01L21/338

CPC分类号： H01L21/0237 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02573 ,  H01L21/02631 ,  H01L29/78606 ,  H01L29/7869

摘要： Provided is a method of fabricating a thin film transistor including source and drain electrodes, a novel channel layer, a gate insulating layer, and a gate electrode, which are formed on a substrate. The method includes the steps of forming the channel layer using an oxide semiconductor doped with boron; and patterning the channel layer. The channel layer formed is an oxide semiconductor thin film doped with boron. The electrical characteristics and high temperature stability of the thin film transistor are improved remarkably.

摘要翻译： 提供了一种制造薄膜晶体管的方法，该薄膜晶体管包括形成在基板上的源电极和漏电极，新颖的沟道层，栅极绝缘层和栅极电极。 该方法包括使用掺杂有硼的氧化物半导体形成沟道层的步骤; 并图形化沟道层。 形成的沟道层是掺杂有硼的氧化物半导体薄膜。 薄膜晶体管的电特性和高温稳定性显着提高。

公开(公告)号：US06693294B1

公开(公告)日：2004-02-17

申请号：US10331945

申请日：2002-12-31

申请人： Moon-Gyu Jang ,  Seong-Jae Lee ,  Woo-Seok Cheong ,  Won-Ju Cho ,  Kyoung-Wan Park

发明人： Moon-Gyu Jang ,  Seong-Jae Lee ,  Woo-Seok Cheong ,  Won-Ju Cho ,  Kyoung-Wan Park

IPC分类号： H01L3900

CPC分类号： H01L29/42384 ,  H01L29/458 ,  H01L29/7839 ,  H01L29/78609 ,  H01L29/78696

摘要： Provided are a Schottky barrier tunnel transistor (SBTT) and a method of fabricating the same. The SBTT includes a buried oxide layer formed on a base substrate layer and having a groove at its upper surface; an ultra-thin silicon-on-insulator (SOI) layer formed across the groove; an insulating layer wrapping the SOI layer on the groove; a gate formed to be wider than the groove on the insulating layer; source and drain regions each positioned at both sides of the gate, the source and drain regions formed of silicide; and a conductive layer for filling the groove. In the SBTT, the SOI layer is formed to an ultra-thin thickness to minimize the occurrence of a leakage current, and a channel in the SOI layer below the gate is completely wrapped by the gate and the conductive layer, thereby improving the operational characteristics of the SBTT.

摘要翻译： 提供了一种肖特基势垒隧道晶体管（SBTT）及其制造方法。 SBTT包括形成在基底层上并在其上表面具有凹槽的掩埋氧化物层; 跨越沟槽形成的超薄绝缘体上硅（SOI）层; 将SOI层包裹在槽上的绝缘层; 形成为比绝缘层上的沟槽宽的栅极; 源极和漏极区域各自位于栅极的两侧，源极和漏极区域由硅化物形成; 以及用于填充凹槽的导电层。 在SBTT中，SOI层形成为超薄的厚度，以最小化泄漏电流的发生，栅极下方的SOI层中的沟道被栅极和导电层完全包围，从而提高了操作特性 的SBTT。

公开(公告)号：US08572546B2

公开(公告)日：2013-10-29

申请号：US13371487

申请日：2012-02-13

申请人： Jaeheon Shin ,  Woo-Seok Cheong ,  Chi-Sun Hwang ,  Sung Mook Chung

发明人： Jaeheon Shin ,  Woo-Seok Cheong ,  Chi-Sun Hwang ,  Sung Mook Chung

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： Methods of modeling a transistor are provided. The method includes the steps of (a) extracting reference mobility values of a channel layer of a transistor including a gate electrode, a source region and a drain region using a reference gate voltage, a reference drain current and a reference drain voltage, (b) fitting a mobility function including model parameters on the reference mobility values to extract the model parameters, and (c) putting the extracted model parameters into a drain current modeling function to calculate a drain current flowing through the channel layer between the drain region and the source region under a bias condition defined by an arbitrary gate voltage applied to the gate electrode and an arbitrary drain voltage applied to the drain region. Related apparatuses are also provided.

摘要翻译： 提供了对晶体管进行建模的方法。 该方法包括以下步骤：（a）使用参考栅极电压，参考漏极电流和参考漏极电压提取包括栅电极，源区和漏区的晶体管的沟道层的参考迁移率值，（b ）将包括模型参数的移动性函数拟合在参考迁移率值上以提取模型参数，以及（c）将所提取的模型参数放入漏极电流建模函数中以计算流过漏极区域和漏极区域之间的沟道层的漏极电流 源极区域由施加到栅极电极的任意栅极电压和施加到漏极区域的任意漏极电压限定的偏置状态。 还提供了相关装置。

公开(公告)号：US20120090543A1

公开(公告)日：2012-04-19

申请号：US13182590

申请日：2011-07-14

申请人： Woo-Seok CHEONG

发明人： Woo-Seok CHEONG

IPC分类号： C23C16/44 ,  B25J18/00 ,  B25J15/06

CPC分类号： C23C16/4587 ,  C23C14/34 ,  C23C14/568 ,  H01L21/67173 ,  H01L21/67712 ,  H01L21/67718 ,  H01L21/67751 ,  H01L21/6776

摘要： Provided is a thin film depositing apparatus. The thin film depositing apparatus includes: a loading chamber loading a plurality of substrates; a first process chamber connected to the loading chamber and including a plurality of sputter guns inducing a first plasma on the plurality of substrates; a buffer chamber connected to the other side of the first process chamber facing the loading chamber; and a substrate transfer module simultaneously passing the plurality of substrates between the plurality of sputter guns during a process using the first plasma and transferring the plurality of substrates from the first process chamber to the buffer chamber.

摘要翻译： 提供了一种薄膜沉积设备。 薄膜沉积设备包括：装载多个基板的装载室; 连接到所述装载室并包括多个溅射枪的第一处理室，所述多个溅射枪在所述多个基板上引入第一等离子体; 连接到所述第一处理室的面向所述装载室的另一侧的缓冲室; 以及基板转移模块，在使用第一等离子体的工艺中将多个基板同时通过多个溅射枪之间并将多个基板从第一处理室传送到缓冲室。

公开(公告)号：US07989286B2

公开(公告)日：2011-08-02

申请号：US12517803

申请日：2007-11-27

申请人： Woo Seok Cheong ,  Jin Ho Lee

发明人： Woo Seok Cheong ,  Jin Ho Lee

IPC分类号： H01L21/8242

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/78 ,  H01L51/0048 ,  H01L51/057

摘要： Provided are an electronic device to which vertical carbon nanotubes (CNTs) are applied and a method of manufacturing the same. The method of manufacturing an electronic device having a vertical CNT includes the steps of: (a) preparing a substrate on which a silicon source is formed; (b) forming a first insulating layer on the substrate, and etching the first insulating layer such that a top surface of the silicon source is exposed; (c) forming a second insulating layer on the silicon source, and forming a gate by patterning the second insulating layer; (d) forming a third insulating layer on the gate, and forming a through hole in which a carbon nanotube channel is to be formed by etching the third insulating layer and the second insulating layer; (e) forming a fourth insulating layer surrounding the gate on the through hole and the third insulating layer, and forming a spacer by etching the fourth insulating layer; (f) forming a metal catalyst on the silicon source; (g) vertically growing the carbon nanotube channel on the silicon source using the metal catalyst; (h) forming a fifth insulating layer on the through hole in which the carbon nanotube is formed and the third insulating layer; and (i) patterning the fifth insulating layer such that the carbon nanotube channel is exposed, and forming a silicon drain. An arrangement problem of horizontal CNTs can be solved by applying vertical CNTs and a selective silicon growth technique.

摘要翻译： 提供了应用立式碳纳米管（CNT）的电子装置及其制造方法。 制造具有垂直CNT的电子器件的方法包括以下步骤：（a）制备其上形成有硅源的衬底; （b）在所述基板上形成第一绝缘层，并且蚀刻所述第一绝缘层以使所述硅源的顶表面露出; （c）在所述硅源上形成第二绝缘层，并且通过图案化所述第二绝缘层形成栅极; （d）在栅极上形成第三绝缘层，形成通过蚀刻第三绝缘层和第二绝缘层形成碳纳米管通道的通孔; （e）在所述通孔和所述第三绝缘层上形成围绕所述栅极的第四绝缘层，并且通过蚀刻所述第四绝缘层形成间隔物; （f）在硅源上形成金属催化剂; （g）使用金属催化剂使硅源上的碳纳米管通道垂直生长; （h）在其上形成有碳纳米管的通孔和第三绝缘层上形成第五绝缘层; 和（i）对第五绝缘层进行构图，使得碳纳米管通道露出，并形成硅漏极。 水平CNT的布置问题可以通过应用垂直CNT和选择性硅生长技术来解决。

公开(公告)号：US20110140097A1

公开(公告)日：2011-06-16

申请号：US12887282

申请日：2010-09-21

申请人： Woo Seok CHEONG ,  Sung Mook Chung ,  Jun Yong Bak

发明人： Woo Seok CHEONG ,  Sung Mook Chung ,  Jun Yong Bak

IPC分类号： H01L29/786 ,  H01L29/22 ,  H01L21/44

CPC分类号： H01L29/66742 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869

摘要： Provided are a thin film transistor in which an oxide semiconductor combined with a nitride containing boron or aluminum is applied to a channel layer and a method of fabricating the same. The thin film transistor in which an oxide semiconductor combined with a nitride containing boron or aluminum is applied to a channel layer exhibits significantly improved mobility and increased stability at a high temperature.

摘要翻译： 提供了一种薄膜晶体管及其制造方法，其中与含有硼或铝的氮化物结合的氧化物半导体被施加到沟道层。 其中与含有硼或铝的氮化物结合的氧化物半导体施加到沟道层的薄膜晶体管显示出显着改善的迁移率和在高温下增加的稳定性。

公开(公告)号：US20100006837A1

公开(公告)日：2010-01-14

申请号：US12496558

申请日：2009-07-01

申请人： Doo Hee Cho ,  Sang Hee Park ,  Chi Sun Hwang ,  Hye Yong Chu ,  Kyoung Ik Cho ,  Shin Hyuk Yang ,  Chun Won Byun ,  Eun Suk Park ,  Oh Sang Kwon ,  Min Ki Ryu ,  Jae Heon Shin ,  Woo Seok Cheong ,  Sung Mook Chung ,  Jeong Ik Lee

发明人： Doo Hee Cho ,  Sang Hee Park ,  Chi Sun Hwang ,  Hye Yong Chu ,  Kyoung Ik Cho ,  Shin Hyuk Yang ,  Chun Won Byun ,  Eun Suk Park ,  Oh Sang Kwon ,  Min Ki Ryu ,  Jae Heon Shin ,  Woo Seok Cheong ,  Sung Mook Chung ,  Jeong Ik Lee

IPC分类号： H01L29/786 ,  H01L21/336 ,  H01B1/08

CPC分类号： H01L29/7869 ,  C23C14/08 ,  H01L29/247

摘要： Provided are a composition for an oxide semiconductor thin film, a field effect transistor using the same and a method of fabricating the field effect transistor. The composition includes an aluminum oxide, a zinc oxide, an indium oxide and a tin oxide. The thin film formed of the composition is in amorphous phase. The field effect transistor having an active layer formed of the composition can have an improved electrical characteristic and be fabricated by a low temperature process.

摘要翻译： 提供了一种用于氧化物半导体薄膜的组合物，使用该组合物的场效应晶体管和制造场效应晶体管的方法。 该组合物包括氧化铝，氧化锌，氧化铟和氧化锡。 由组合物形成的薄膜是非晶相。 具有由组合物形成的有源层的场效应晶体管可以具有改进的电特性并通过低温工艺制造。

公开(公告)号：US09331218B2

公开(公告)日：2016-05-03

申请号：US13614815

申请日：2012-09-13

申请人： Woo-Seok Cheong ,  Rae-Man Park

发明人： Woo-Seok Cheong ,  Rae-Man Park

IPC分类号： H01L21/00 ,  H01L31/0224 ,  H01L31/0749 ,  H01L31/046 ,  H01L31/0465

CPC分类号： H01L31/022466 ,  H01L31/022483 ,  H01L31/046 ,  H01L31/0465 ,  H01L31/0749 ,  Y02E10/541 ,  Y02P70/521

摘要： Provided are a solar cell module and a method of manufacturing the same. The solar cell module including: a substrate; a bottom electrode layer discontinuously formed on the substrate; a light absorbing layer formed on the bottom electrode layer and including a first trench that exposes the bottom electrode layer; and a transparent electrode layer extending from the top of the light absorbing layer to the bottom electrode layer at the bottom of the first trench, and including a first oxide layer, a metal layer, and a second oxide layer, all of which are staked on the light absorbing layer and the bottom electrode layer.

摘要翻译： 提供一种太阳能电池模块及其制造方法。 太阳能电池模块包括：基板; 在基板上不连续地形成的底部电极层; 形成在所述底部电极层上并包括暴露所述底部电极层的第一沟槽的光吸收层; 以及透明电极层，其从所述光吸收层的顶部延伸到所述第一沟槽的底部的所述底部电极层，并且包括第一氧化物层，金属层和第二氧化物层，所述第一氧化物层， 光吸收层和底电极层。