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48 条记录 (耗时 0.024 秒)

    LED MODULE, METHOD FOR MANUFACTURING THE SAME, AND LED CHANNEL LETTER INCLUDING THE SAME
    11.
    发明申请
    LED MODULE, METHOD FOR MANUFACTURING THE SAME, AND LED CHANNEL LETTER INCLUDING THE SAME 有权
    LED模块，其制造方法和包括其的LED通道信号

    公开(公告)号：US20120228649A1

    公开(公告)日：2012-09-13

    申请号：US13416540

    申请日：2012-03-09

    申请人： Woo Seok KIM ,  Jae Young CHOI ,  Kyu Won HAN ,  Eun Jung KIM

    发明人： Woo Seok KIM ,  Jae Young CHOI ,  Kyu Won HAN ,  Eun Jung KIM

    IPC分类号： H01L33/58 ,  H01L33/08 ,  H01L33/52 ,  H01L33/48

    CPC分类号： H01L33/486 ,  F21K9/00 ,  F21K9/90 ,  F21Y2115/10 ,  G09F9/33 ,  H01L33/62 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed herein is a method for manufacturing a light emitting diode (LED) module, the method including: disposing a circuit board at a molding space formed by an upper mold and a lower mold; adding a filling material to the molding space; hardening the filling material to form a molding cover covering at least a portion of an upper surface, a lower surface, and a side surface of the circuit board, the molding cover having an opening exposing the lower surface of the circuit board; removing the upper mold and the lower mold from the circuit board; and disposing an LED on the upper surface of the circuit board.

    摘要翻译： 本发明公开了一种制造发光二极管（LED）模块的方法，该方法包括：将电路板设置在由上模和下模形成的模制空间中; 向成型空间添加填充材料; 硬化填充材料以形成覆盖电路板的上表面，下表面和侧表面的至少一部分的模制盖，模制盖具有暴露电路板的下表面的开口; 从电路板上拆下上模和下模; 以及在所述电路板的上表面上配置LED。

    Superconducting power transforming apparatus
    12.
    发明授权
    Superconducting power transforming apparatus 有权
    超导电力变压装置

    公开(公告)号：US08089332B2

    公开(公告)日：2012-01-03

    申请号：US12679697

    申请日：2009-11-19

    申请人： Kyeong-Dal Choi ,  Ji-Kwang Lee ,  Woo-Seok Kim ,  Chan Park ,  Sun-Bok Choi

    发明人： Kyeong-Dal Choi ,  Ji-Kwang Lee ,  Woo-Seok Kim ,  Chan Park ,  Sun-Bok Choi

    IPC分类号： H01F27/02

    CPC分类号： H01F36/00 ,  H01F6/065 ,  Y02E40/66

    摘要： The present invention relates to a superconducting power transforming apparatus. The superconducting power transforming apparatus according to the present invention comprises a transformer housing having a transforming cable passing hole and filled with a liquid cooling means; a superconducting transformer housed in the transformer housing in a state that the superconducting transformer is immersed in the liquid cooling means; a tap changer housing having a tap changing cable passing hole and vacuum-sealed from outside; a power tap changer housed in the vacuum tap changer housing; and a cable linking pipe vacuum-sealed from the transformer housing and the tap changer housing, and linking the transforming cable passing hole with the tap changing passing hole in order that a transformer winding tap cable connecting the superconducting transformer and the power tap changer passes through. Consequently, it is possible to guarantee stable operation of a superconducting transformer which works at an extremely low temperature and a power tap changer as like On-Load Tap Changer which works at low temperature.

    摘要翻译： 本发明涉及一种超导功率变换装置。 根据本发明的超导电力变换装置包括具有变换电缆通孔并且充满液体冷却装置的变压器壳体; 以超导变压器浸入液体冷却装置的状态容纳在变压器外壳中的超导变压器; 分接开关壳体，具有抽头更换电缆通孔并从外部真空密封; 一个容纳在真空分接开关壳体中的电源分接开关; 以及从变压器壳体和分接开关壳体真空密封的电缆连接管，并将变压电缆通孔与抽头更换通孔相连接，以便连接超导变压器和电源分接开关的变压器绕组电缆通过 。 因此，可以保证在极低温度下工作的超导变压器的稳定运行，以及在低温工作的有载分接开关的功率抽头变换器。

    BACKLIGHT UNIT AND DISPLAY APPARATUS HAVING THE SAME
    14.
    发明申请
    BACKLIGHT UNIT AND DISPLAY APPARATUS HAVING THE SAME 审中-公开
    背光单元和显示装置

    公开(公告)号：US20110249036A1

    公开(公告)日：2011-10-13

    申请号：US13071910

    申请日：2011-03-25

    申请人： Woo-Seok KIM

    发明人： Woo-Seok KIM

    IPC分类号： G09G5/10

    CPC分类号： G09G3/342 ,  G09G2320/064 ,  G09G2330/02 ,  G09G2330/025 ,  H05B33/0818 ,  H05B33/0845

    摘要： Provided are a backlight unit and a display apparatus including the same. The display apparatus includes a display panel, a light emitting unit including a plurality of channels, each channel including light emitting diodes configured to irradiate light to the display panel, and a plurality of switches configured to enable current paths of the channels in response to switching signals, and a driver circuit configured to successively enable the switching signals corresponding to the respective channels, compare the duty ratio of the switching signals with 1/channel number, and selectively control the phases of the switching signals based on the comparison result.

    摘要翻译： 提供一种背光单元和包括该背光单元的显示装置。 显示装置包括显示面板，包括多个通道的发光单元，每个通道包括被配置为向显示面板照射光的发光二极管，以及多个开关，其被配置为响应于切换而使通道的电流路径 信号和驱动电路，其被配置为连续启用与各个通道相对应的开关信号，将开关信号的占空比与1 /通道数进行比较，并且基于比较结果选择性地控制开关信号的相位。

    MULTIPLE TRANSPOSITION METHOD FOR SUPERCONDUCTING WIRE
    15.
    发明申请
    MULTIPLE TRANSPOSITION METHOD FOR SUPERCONDUCTING WIRE 有权
    用于超导线的多种传输方法

    公开(公告)号：US20110239443A1

    公开(公告)日：2011-10-06

    申请号：US12997652

    申请日：2010-07-05

    申请人： Kyeong Dal Choi ,  Ji K wang Lee ,  Woo Seok Kim ,  Chan Park ,  Yung II Kim

    发明人： Kyeong Dal Choi ,  Ji K wang Lee ,  Woo Seok Kim ,  Chan Park ,  Yung II Kim

    IPC分类号： H01L39/24

    CPC分类号： H01B12/02 ,  H01B7/306 ,  Y02E40/641 ,  Y10T29/49014 ,  Y10T29/49194

    摘要： Provided is a multiple transposition method for superconducting wire, by making each superconducting wire unit from second-generation superconducting wires that were firstly transposed and then transposing each superconducting wire unit in such a manner that the phase of each unit can be changed along the length, comprising preparing wires by making curves on superconducting wires in such a manner that the superconducting wires of a thin multiple layer grown epitaxially are slit in zigzags and then making the curves repeatedly and by machining the wires with a desired length; making first-transposed superconducting wire units by combining a plurality of the prepared wires such that curves of adjacent wires come in touch to each other and are superposed; preparing a superconducting wire unit bundle by arranging the first-transposed superconducting wires units and by locating a plurality of the first-transposed superconducting wire units in parallel along the length; and making a second transposition on the first-transposed superconducting wire units by rotating the plurality of superconducting wire units on the central axis of the superconducting wire unit bundle along the length to be twisted and combined with each other.

    摘要翻译： 提供了一种用于超导线的多重转置方法，通过使来自第二代超导线的每个超导线单元首先被转置，然后以每个单元的相位沿着该长度改变的方式移位每个超导线单元， 包括通过在超导线上制作曲线来制备导线，使得外延生长的薄多层的超导线以锯齿形切割，然后反复制作曲线并通过机加工所需长度的线; 通过组合多个所制备的导线使相邻导线的曲线彼此接触并重叠而制造第一转置超导线单元; 通过布置第一转置超导线单元并通过沿着长度平行地定位多个第一转置的超导线单元来制备超导线单元束; 以及通过在所述超导线单元束的中心轴线上沿着要被扭曲并且彼此组合的长度旋转所述多个超导线单元，在所述第一转置的超导线单元上进行第二转置。

    Clock multiplier and method of multiplying a clock
    16.
    发明授权
    Clock multiplier and method of multiplying a clock 有权
    时钟乘法器和乘法时钟的方法

    公开(公告)号：US07636002B2

    公开(公告)日：2009-12-22

    申请号：US11840515

    申请日：2007-08-17

    申请人： Woo-Seok Kim

    发明人： Woo-Seok Kim

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0812 ,  H03L7/0891 ,  H03L7/18

    摘要： A clock multiplier for multiplying an input clock by N includes a phase/frequency detector, a clock selector, and a voltage-controlled delay line. The phase/frequency detector generates a first control signal and a second control signal according to a frequency/phase difference between the input clock and a count signal indicating a signal that is generated by delaying the input clock N times. The clock selector selects one of the input clock and a feedback clock based on the input clock and the count signal. The voltage-controlled delay line adjusts a delay time of the selected signal according to a control voltage that is generated based on the first control signal and the second control signal, and outputs the feedback clock based on the adjusted signal. The clock multiplier operates without accumulating a frequency/phase difference between the input clock and the output clock when the multiplying ratio is increased.

    摘要翻译： 用于将输入时钟乘以N的时钟乘法器包括相位/频率检测器，时钟选择器和电压控制延迟线。 相位/频率检测器根据输入时钟与指示通过延迟输入时钟N次而产生的信号的计数信号之间的频率/相位差产生第一控制信号和第二控制信号。 时钟选择器根据输入时钟和计数信号选择输入时钟和反馈时钟之一。 电压控制延迟线根据基于第一控制信号和第二控制信号产生的控制电压来调整所选信号的延迟时间，并且基于调整后的信号输出反馈时钟。 当倍频比增加时，时钟倍频器不会累积输入时钟和输出时钟之间的频率/相位差。

    Phase-locked loop circuit, delay-locked loop circuit and method of tuning output frequencies of the same
    17.
    发明授权
    Phase-locked loop circuit, delay-locked loop circuit and method of tuning output frequencies of the same 失效
    锁相环电路，延迟锁定环路电路及其调谐输出频率的方法

    公开(公告)号：US07495488B2

    公开(公告)日：2009-02-24

    申请号：US11712034

    申请日：2007-02-28

    申请人： Woo-Seok Kim

    发明人： Woo-Seok Kim

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0812 ,  H03L7/0995 ,  H03L7/10 ,  H03L2207/06

    摘要： A phase-locked loop (PLL) circuit includes a phase/frequency detector (PFD), a charge pump, a loop filter, a control circuit, a VCO, and a feedback circuit. The control circuit generates a digital control signal in response to the up signal, the down signal, and the oscillation-control voltage. The VCO generates an output signal of which a frequency is changed in response to the oscillation-control voltage and the digital control signal. Accordingly, the PLL circuit can automatically tune the frequency of the output signal of a VCO using a digital circuit having a simple structure.

    摘要翻译： 锁相环（PLL）电路包括相位/频率检测器（PFD），电荷泵，环路滤波器，控制电路，VCO和反馈电路。 控制电路响应于上升信号，下降信号和振荡控制电压产生数字控制信号。 VCO产生响应于振荡控制电压和数字控制信号改变频率的输出信号。 因此，PLL电路可以使用具有简单结构的数字电路来自动调谐VCO的输出信号的频率。

    Voltage-controlled oscillators with controlled operating range and related bias circuits and methods
    18.
    发明授权
    Voltage-controlled oscillators with controlled operating range and related bias circuits and methods 失效
    具有受控工作范围和相关偏置电路和方法的压控振荡器

    公开(公告)号：US07233214B2

    公开(公告)日：2007-06-19

    申请号：US11198691

    申请日：2005-08-05

    申请人： Woo-Seok Kim ,  Ju-Hyung Kim

    发明人： Woo-Seok Kim ,  Ju-Hyung Kim

    IPC分类号： H03L1/02 ,  H03L7/099

    CPC分类号： H03L7/0995 ,  H03K3/0322 ,  H03K5/2472 ,  H03L1/022 ,  H03L7/099

    摘要： A voltage-controlled oscillator includes a bias circuit and a delay circuit. The bias circuit may generate a bias voltage signal pair having levels that are based on the voltage level of an input voltage signal and that are constrained by the values of a maximum current signal and a minimum current signal that are generated in the bias circuit. The delay circuit generates an output signal having a frequency that varies in response to the bias voltage signal pair. Because an operating frequency range of a voltage-controlled oscillator VCO is limited by a bias circuit, the VCO can operate with reduced gain and can limit the maximum operating frequency to a predetermined level. The VCO may also include a PTAT current generator in the bias circuit which can allow the VCO to compensate for variations of the VCO output frequency based on temperature.

    摘要翻译： 压控振荡器包括偏置电路和延迟电路。 偏置电路可以产生具有基于输入电压信号的电压电平并且受偏置电路中产生的最大电流信号和最小电流信号的值约束的电平的偏置电压信号对。 延迟电路产生具有响应于偏置电压信号对而变化的频率的输出信号。 由于压控振荡器VCO的工作频率范围由偏置电路限制，所以VCO可以以减小的增益进行工作，并且可以将最大工作频率限制在预定的水平。 VCO还可以包括偏置电路中的PTAT电流发生器，其可以允许VCO基于温度补偿VCO输出频率的变化。

    Phase-locked loop circuit having phase lock detection function and method for detecting phase lock thereof
    19.
    发明授权
    Phase-locked loop circuit having phase lock detection function and method for detecting phase lock thereof 有权
    具有相位锁定检测功能的锁相环电路及其相位锁定检测方法

    公开(公告)号：US07116145B2

    公开(公告)日：2006-10-03

    申请号：US10960367

    申请日：2004-10-06

    申请人： Woo-Seok Kim ,  Phil-Jae Jeon

    发明人： Woo-Seok Kim ,  Phil-Jae Jeon

    IPC分类号： H03L7/06

    CPC分类号： H03L7/095 ,  H03L7/0891

    摘要： A phase-locked loop circuit including a lock detection function is disclosed. The phase-locked loop circuit comprises a lock detection circuit. The lock detection circuit includes a lock-detection-start-signal generator, a lock-detection-clock generator, and a lock-detection-signal generator. The lock-detection-start-signal generates a lock detection start signal when the pulse width of an up signal and a down signal reaches a predetermined value. The lock-detection-clock generator generates a lock detection clock signal on the basis of the up signal and the down signal. The lock-detection-signal generator counts the lock detection clock signal, and generates the lock detection signal. The phase-locked loop circuit is capable of discriminating the operating regions thereof and outputting a lock detection signal when the locking of phase is completed.

    摘要翻译： 公开了一种包括锁定检测功能的锁相环电路。 锁相环电路包括锁定检测电路。 锁定检测电路包括锁定检测启动信号发生器，锁定检测时钟发生器和锁定检测信号发生器。 当上升信号和下降信号的脉冲宽度达到预定值时，锁定检测启动信号产生锁定检测开始信号。 锁定检测时钟发生器基于上行信号和下降信号产生锁定检测时钟信号。 锁定检测信号发生器对锁定检测时钟信号进行计数，并产生锁定检测信号。 当相位锁定完成时，锁相环电路能够识别其工作区域并输出锁定检测信号。