公开(公告)号：US20100173485A1

公开(公告)日：2010-07-08

申请号：US12458675

申请日：2009-07-20

申请人： Seung-jun Lee ,  Woon-kyung Lee ,  Seung-wan Hong

发明人： Seung-jun Lee ,  Woon-kyung Lee ,  Seung-wan Hong

IPC分类号： H01L21/28 ,  H01L21/3205

CPC分类号： H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11568

摘要： A method of manufacturing a non-volatile memory device providing a semiconductor layer in which a cell region and a peripheral region are defined, sequentially forming a first insulating layer, a first conductive layer, a second insulating layer, and a second conductive layer on the cell region and the peripheral region, forming a trench for exposing a portion of the first conductive layer of the peripheral region, wherein the trench is formed by removing portions of the second conductive layer and the second insulating layer in the peripheral region, performing a trimming operation for removing portions of the second conductive layer and the second insulating layer of the cell region, forming a spacer on a side surface of the trench, and forming a silicide layer that is electrically connected to the first conductive layer, wherein the silicide layer is formed by performing a silicidation process on the spacer.

摘要翻译： 一种制造提供其中限定了单元区域和外围区域的半导体层的非易失性存储器件的方法，其顺序地形成在第一绝缘层，第一导电层，第二绝缘层和第二导电层上 形成用于暴露周边区域的第一导电层的一部分的沟槽，其中通过去除周边区域中的第二导电层和第二绝缘层的部分形成沟槽，进行修整 用于去除所述单元区域的所述第二导电层和所述第二绝缘层的部分的工作，在所述沟槽的侧表面上形成间隔物，以及形成电连接到所述第一导电层的硅化物层，其中所述硅化物层为 通过在间隔物上进行硅化处理而形成。

公开(公告)号：US20100140720A1

公开(公告)日：2010-06-10

申请号：US12631109

申请日：2009-12-04

申请人： Dongyean Oh ,  Woon-kyung Lee

发明人： Dongyean Oh ,  Woon-kyung Lee

IPC分类号： H01L27/088

CPC分类号： H01L27/088 ,  H01L21/823462 ,  H01L21/823493

摘要： Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device can include first transistors that include a first gate insulating layer having a first thickness and second transistors include a second gate insulating layer having a second thickness less than the first thickness. At least one of the transistors formed on the first or second gate insulating layers is directly over a dummy well.

摘要翻译： 提供半导体器件和制造半导体器件的方法。 半导体器件可以包括第一晶体管，其包括具有第一厚度的第一栅极绝缘层，第二晶体管包括具有小于第一厚度的第二厚度的第二栅极绝缘层。 形成在第一或第二栅极绝缘层上的晶体管中的至少一个直接在虚拟阱上。

公开(公告)号：US20090296477A1

公开(公告)日：2009-12-03

申请号：US12437209

申请日：2009-05-07

申请人： Jong-Won Kim ,  Woon-Kyung Lee

发明人： Jong-Won Kim ,  Woon-Kyung Lee

IPC分类号： G11C16/04 ,  H01L29/788 ,  H01L29/792 ,  G11C7/02

CPC分类号： H01L27/11568 ,  H01L27/11521 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate including a cell array region, memory cell transistors disposed at the cell array region, bitlines disposed on the memory cell transistors, and a source plate disposed between the memory cell transistors and the bitlines to veil the memory cell transistors thereunder.

摘要翻译： 提供半导体器件及其制造方法。 半导体器件包括：半导体衬底，包括单元阵列区域，设置在单元阵列区域的存储单元晶体管，设置在存储单元晶体管上的位线;以及设置在存储单元晶体管和位线之间的源极，以对存储单元晶体管 在那里

公开(公告)号：US07592664B2

公开(公告)日：2009-09-22

申请号：US11653865

申请日：2007-01-17

申请人： Woon Kyung Lee

发明人： Woon Kyung Lee

IPC分类号： H01L29/76 ,  H01L29/788

CPC分类号： H01L29/7881 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/42336 ,  H01L29/513

摘要： Example embodiments are directed to a method of forming a nonvolatile memory structure and a nonvolatile memory structure including a plurality of charge storage patterns, wherein an electrical coupling distance (Lc) between adjacent charge storage patterns is larger than a direct geometric distance (Ls) between adjacent charge storage patterns.

摘要翻译： 示例性实施例涉及形成非易失性存储器结构和包括多个电荷存储图案的非易失性存储器结构的方法，其中相邻电荷存储图案之间的电耦合距离（Lc）大于相邻电荷存储模式之间的直接几何距离（L s） 相邻的电荷存储模式。

公开(公告)号：US20070001215A1

公开(公告)日：2007-01-04

申请号：US11480729

申请日：2006-07-03

申请人： Jong-Kwang Llm ,  Jeong-Hyuk Choi ,  Woon-Kyung Lee ,  Jai-Hyuk Song

发明人： Jong-Kwang Llm ,  Jeong-Hyuk Choi ,  Woon-Kyung Lee ,  Jai-Hyuk Song

IPC分类号： H01L29/788

CPC分类号： H01L29/42324 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/40114

摘要： A nonvolatile memory device includes a device isolating layer disposed at a substrate to define an active region and a floating gate disposed on the active region. The floating gate includes a flat portion and a pair of wall portions. The pair of wall portions extend upward from both edges of the flat portion adjacent to the device isolating layer and face each other. The nonvolatile memory device further includes a tunnel insulating layer interposed between the floating gate and the active region. Moreover, the wall portions and the flat portion are formed of a single layer, and the thickness of the flat portion is larger than a width of the wall portions.

摘要翻译： 非易失性存储器件包括设置在衬底上以限定有源区的器件隔离层和布置在有源区上的浮置栅。 浮动门包括平坦部分和一对壁部分。 所述一对壁部分从邻近所述装置隔离层的所述平坦部分的两个边缘向上延伸并面对彼此。 非易失性存储器件还包括插入在浮置栅极和有源区域之间的隧道绝缘层。 此外，壁部和平坦部由单层形成，平坦部的厚度大于壁部的宽度。

公开(公告)号：US06933195B2

公开(公告)日：2005-08-23

申请号：US09995299

申请日：2001-11-27

申请人： Woon-kyung Lee

发明人： Woon-kyung Lee

IPC分类号： H01L27/115 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11543

摘要： A method of fabricating a flash memory device includes forming a device isolation layer at a predetermined region of a semiconductor substrate having a cell array region and a peripheral circuit region. The device isolation layer defines a first active region and a second active region in the cell array region and the peripheral circuit region, respectively. A gate conductive layer is formed on the entire surface of the semiconductor substrate having the device isolation layer. The gate conductive layer is patterned to form a floating gate pattern covering the first active region. At this time, the peripheral circuit region is still covered with the gate conductive layer. An inter-gate dielectric layer and a control gate conductive layer are formed on the entire surface of the substrate including the floating gate pattern. The control gate conductive layer and the inter-gate dielectric layer, which are located in the peripheral circuit region, are selectively removed to expose the gate conductive layer in the peripheral circuit region.

摘要翻译： 制造闪存器件的方法包括在具有单元阵列区域和外围电路区域的半导体衬底的预定区域形成器件隔离层。 器件隔离层分别在单元阵列区域和外围电路区域中限定第一有源区和第二有源区。 在具有器件隔离层的半导体衬底的整个表面上形成栅极导电层。 图案化栅极导电层以形成覆盖第一有源区的浮栅图案。 此时，外围电路区域仍然被栅极导电层覆盖。 在包括浮置栅极图案的衬底的整个表面上形成栅极间电介质层和控制栅极导电层。 选择性地去除位于外围电路区域中的控制栅极导电层和栅极间电介质层，以露出外围电路区域中的栅极导电层。

公开(公告)号：US06573574B2

公开(公告)日：2003-06-03

申请号：US10178626

申请日：2002-06-24

申请人： Woon-Kyung Lee

发明人： Woon-Kyung Lee

IPC分类号： H01L2976

CPC分类号： H01L27/11266 ,  G11C17/126 ,  H01L27/112 ,  Y10S257/908

摘要： In a cell array region of a NOR-type mask ROM device and a fabricating method therefor, following formation of a plurality of word lines parallel to one another on a semiconductor substrate, a plurality of sub-bit lines intersecting the top portion of the plurality of word lines at right angles are formed. Trench regions are formed on the semiconductor substrate exposed by the plurality of word lines and the plurality of sub-bit lines. An interlayer insulating layer is formed on the entire surface of the resulting material, and a plurality of bit lines which are parallel to one another are formed on the interlayer insulating layer.

公开(公告)号：US06555865B2

公开(公告)日：2003-04-29

申请号：US09902820

申请日：2001-07-10

申请人： Joon-Sung Lee ,  Woon-Kyung Lee

发明人： Joon-Sung Lee ,  Woon-Kyung Lee

IPC分类号： H01L2976

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11543 ,  H01L29/42324 ,  H01L29/792

摘要： The present invention provides a nonvolatile memory device having high reliability with novel sidewall spacer structures. The gate stack structure for use in a nonvolatile memory device comprises a semiconductor substrate, a gate stack formed on the semiconductor substrate. The gate stack has a sidewall and a top surface. A multi-layer sidewall spacer structure is formed on the sidewall of the gate stack. The multi-layer sidewall spacer structure includes a first oxide layer, a first nitride layer, a second oxide layer, and a second nitride layer that are sequentially stacked. With the present invention, even if the second nitride layer is perforated or damaged during the formation of contact holes, sidewalls of the gate stack of nonvolatile memory cell can be protected with the first nitride layer from mobile ions. Also, etching damage to source/drain regions or field regions can be reduced.

摘要翻译： 本发明提供一种具有高可靠性的新型侧壁间隔结构的非易失性存储器件。 用于非易失性存储器件的栅极堆叠结构包括半导体衬底，形成在半导体衬底上的栅叠层。 栅极堆叠具有侧壁和顶部表面。 在栅叠层的侧壁上形成多层侧壁间隔结构。 多层侧壁间隔结构包括依次堆叠的第一氧化物层，第一氮化物层，第二氧化物层和第二氮化物层。 利用本发明，即使在形成接触孔期间第二氮化物层被穿孔或损坏，非易失性存储单元的栅极堆叠的侧壁可以被移动离子的第一氮化物层保护。 此外，可以减少对源极/漏极区域或场区域的蚀刻损伤。

公开(公告)号：US06291308B1

公开(公告)日：2001-09-18

申请号：US09372850

申请日：1999-08-12

申请人： Woon-kyung Lee ,  He-jueng Lee

发明人： Woon-kyung Lee ,  He-jueng Lee

IPC分类号： H01L2176

CPC分类号： H01L27/11293

摘要： A method for fabricating a mask ROM capable of effectively reducing the distance of buried impurity diffusion regions. The method includes stacking a pad oxide layer and a first anti-oxidation layer in sequence in a cell array region and a peripheral circuit region of a semiconductor substrate. The anti-oxidation layer is partially etched to form a first pattern defining an isolation region of the peripheral circuit region and a second pattern defining a buried impurity diffusion region of the cell array region, and a second anti-oxidation layer is stacked, and then the second anti-oxidation layer stacked in the peripheral circuit region is removed, so that the second anti-oxidation layer stacked in the cell array region remains. Then, a field oxide layer is formed in the isolation region of the peripheral circuit region, exposed by the remaining second anti-oxidation layer; and impurities are implanted to form the buried impurity diffusion region.

摘要翻译： 一种制造掩模ROM的方法，其能够有效地减少掩埋的杂质扩散区域的距离。 该方法包括在半导体衬底的单元阵列区域和外围电路区域中依次层叠衬垫氧化物层和第一抗氧化层。 部分蚀刻抗氧化层以形成限定外围电路区域的隔离区域的第一图案和限定电池阵列区域的掩埋杂质扩散区域的第二图案，并且层叠第二抗氧化层，然后 去除在周边电路区域堆叠的第二抗氧化层，从而保留堆叠在电池阵列区域中的第二抗氧化层。 然后，在外围电路区域的隔离区域中形成场氧化物层，由剩余的第二抗氧化层露出; 并且注入杂质以形成掩埋的杂质扩散区域。

公开(公告)号：US5923606A

公开(公告)日：1999-07-13

申请号：US954905

申请日：1997-10-21

申请人： Woon-Kyung Lee ,  Eui-Do Kim

发明人： Woon-Kyung Lee ,  Eui-Do Kim

IPC分类号： H01L21/8246 ,  H01L27/112 ,  G11C13/00

CPC分类号： H01L27/112

摘要： A NOR-type mask ROM reduces the resistance ratio of buried diffusion layers and improves the drive capacity of bank selection transistors by utilizing sub-bit line selection transistors located near the center of a memory cell array. The sub-bit line selection transistors are connected to a pair of sub-bank selection lines that divide the memory cell array into symmetric upper and lower portions. The bank selection transistors couple alternate sub-bit lines to main bit lines at both ends of the sub-bit lines, thereby forming a dual current path between the main bit lines and the memory cells coupled to the sub-bit lines.

摘要翻译： NOR型掩模ROM通过利用位于存储单元阵列中心附近的子位线选择晶体管来降低掩埋扩散层的电阻比，并且提高了存储体选择晶体管的驱动能力。 子位线选择晶体管连接到将存储单元阵列分成对称的上部和下部的一对子组选择线。 存储体选择晶体管将副位线耦合到子位线两端的主位线，从而在主位线和耦合到子位线的存储单元之间形成双电流路径。