公开(公告)号：US5629642A

公开(公告)日：1997-05-13

申请号：US579135

申请日：1995-12-27

Applicant: Yoshimasa Yoshimura

Inventor： Yoshimasa Yoshimura

IPC: H02H3/24 ,  G01R19/165 ,  G05F1/10 ,  G06F1/28 ,  H03K17/00 ,  H03K17/22 ,  H03L7/00 ,  H03K3/02

CPC classification number: H03K17/223 ,  G01R19/16552 ,  G06F1/28 ,  H03K2217/0036

Abstract: In a power supply monitor which outputs a reset signal when the power supply voltage decreases, a first voltage is generated by a first voltage generator in proportion to a power supply voltage, and a comparator supplying a first signal when the first voltage becomes lower than a reference voltage. On the other hand, a slewing rate detector supplies a second signal when a slewing rate of decreasing in power supply voltage is larger than a threshold value. Then, a signal generator supplying a signal set by a trailing edge of the second signal received from the slewing rate detector except a period after the second signal is received and reset by a trailing edge of the first signal received from the comparator. That is, even if the power supply voltage decreases, the monitor does not generate a reset signal when the decrease in the power supply voltage is instantaneous.

Abstract translation: 在电源电压降低时输出复位信号的电源监视器中，与电源电压成比例地由第一电压发生器产生第一电压，以及当第一电压变得低于第一电压时提供第一信号的比较器 参考电压。 另一方面，当电源电压降低的回转速度大于阈值时，回转速率检测器提供第二信号。 然后，信号发生器提供由第二信号接收到的第二信号的后沿的第二信号的后沿设置的信号，除了接收到第二信号之后的周期，并且由从比较器接收到的第一信号的后沿复位。 也就是说，即使电源电压降低，当电源电压的下降是瞬时的时，监视器也不会产生复位信号。

公开(公告)号：US06646917B1

公开(公告)日：2003-11-11

申请号：US10400463

申请日：2003-03-28

Applicant: Yoshimasa Yoshimura

Inventor： Yoshimasa Yoshimura

IPC: G11C1604

CPC classification number: G06F12/0246

Abstract: A flash memory includes a user block for storage of user data, an alternate block reserved for substitution, a conversion table for storage of a physical address of the user block corresponding to a logical address, and an alternate table for storage of a physical address of the alternate block. A controller refers to the conversion table for writing the user data to a page within the user block. If the relevant page has data already written therein, the controller refers to the alternate table and writes the user data to a page within the alternate block to use it as a new user block, and switches the original user block to an alternate block. This permits rapid rewriting of the user data.

Abstract translation: 闪速存储器包括用于存储用户数据的用户块，保留用于替换的备用块，用于存储对应于逻辑地址的用户块的物理地址的转换表以及用于存储逻辑地址的物理地址的备用表 替代块。 控制器是指将用户数据写入用户块内的页面的转换表。 如果相关页面中已经写入了数据，则控制器引用备用表并将用户数据写入替代块中的页面，以将其用作新的用户块，并将原始用户块切换到备用块。 这允许快速重写用户数据。

公开(公告)号：US06546517B1

公开(公告)日：2003-04-08

申请号：US09488676

申请日：2000-01-21

Applicant: Yoshimasa Yoshimura

Inventor： Yoshimasa Yoshimura

IPC: G11C2900

CPC classification number: G11C16/105 ,  G06F8/61 ,  G06F11/10 ,  G11C16/102

Abstract: An external memory includes a RAM of a fixed size for storing firmware, and a flash memory group. Since the flash memory group is accessible on a block-by-block basis, a plurality of program codes each corresponding to one processing routine are individually accessible. The RAM includes a first storage region (91) serving as a dynamic load area to which a program code stored in each block of the flash memory group is exclusively loaded. The exclusive loading of the plurality of program codes each corresponding to the respective one processing routine to the first storage region allows a smaller required size of the RAM. Since the flash memory group is rewritable, the firmware may be subjected to modification and version update. In this case, the required size of the RAM is not increased. Therefore, the external memory can store the firmware of a size exceeding the fixed size of the RAM.

Abstract translation: 外部存储器包括用于存储固件的固定大小的RAM和闪存组。 由于闪存组可以逐块访问，所以每个对应于一个处理例程的多个程序代码可以单独访问。 RAM包括用作存储在闪存组的每个块中的程序代码被独占地加载的动态加载区域的第一存储区域（91）。 每个对应于相应的一个处理例程的多个程序代码的独占加载到第一存储区域允许RAM的较小的所需大小。 由于闪存组是可重写的，所以可以对固件进行修改和版本更新。 在这种情况下，RAM的所需大小不增加。 因此，外部存储器可以存储超过RAM固定大小的固件。

公开(公告)号：US06477547B1

公开(公告)日：2002-11-05

申请号：US09400186

申请日：1999-09-21

Applicant: Yoshimasa Yoshimura

Inventor： Yoshimasa Yoshimura

IPC: G06F1730

CPC classification number: G06F21/445 ,  G06F21/79 ,  Y10S707/99932 ,  Y10S707/99939 ,  Y10S707/99954

Abstract: There is provided a processing system capable of preventing third parties from improper operation. Referring to FIG. 4, a storage device generates a pseudo random number (key data k), calculates a value g (k) of a function g, rearranges each bit of the key data k and value g (k) in accordance with a predetermined method, transmits them to a terminal device, and calculates a value f (k) of a function f. The terminal device receives data and calculates a value g (k). The terminal device compares the value g (k) received from the storage device and the value g (k) calculated by the terminal device. If the values do not match, access to the storage device is stopped. If the values match, the terminal device calculates and transmits value f (k) to the storage device. The storage device compares the value f (k) calculated by the storage device and the value f (k) received from the terminal device and responds to a result of the comparison by determining whether to permit access from the terminal device.

Abstract translation: 提供了能够防止第三方操作不正常的处理系统。 参考图 如图4所示，存储装置生成伪随机数（密钥数据k），计算函数g的值g（k），根据预定方法重新排列密钥数据k的每个比特和值g（k），发送 它们到终端设备，并且计算函数f的值f（k）。 终端装置接收数据并计算值g（k）。 终端装置比较从存储装置接收的值g（k）和终端装置计算的值g（k）。 如果值不匹配，则停止对存储设备的访问。 如果值匹配，则终端设备计算并向存储设备发送值f（k）。 存储装置将由存储装置计算的值f（k）和从终端装置接收的值f（k）进行比较，并通过确定是否允许从终端装置接入来对比较结果进行响应。

公开(公告)号：US06421274B1

公开(公告)日：2002-07-16

申请号：US09983649

申请日：2001-10-25

Applicant: Yoshimasa Yoshimura

Inventor： Yoshimasa Yoshimura

IPC: G11C1604

CPC classification number: G11C7/1087 ,  G11C7/1051 ,  G11C7/1078 ,  G11C8/12 ,  G11C16/06

Abstract: A capacity size of a single block of a flash memory (2) is an integer multiple of a single sector size which is a processing unit of an external host (4), and each of the first and second buffer RAMs interposed between the external host and the flash memory has a capacity corresponding to a single sector size of the flash memory, and data transmission between the external host and the buffer RAMs and between the flash memory and the buffer RAMs are performed by alternately selecting different buffer RAMs, and thus the data transmission between the buffer RAMs and the external host is performed simultaneously. and in parallel with performing the data transmission between the buffer RAMs and the flash memory.

Abstract translation: 闪存（2）的单个块的容量大小是作为外部主机（4）的处理单元的单个扇区大小的整数倍，并且第一和第二缓冲RAM中的每一个插入在外部主机 并且闪速存储器具有对应于闪存的单个扇区大小的容量，并且通过交替地选择不同的缓冲RAM来执行外部主机和缓冲RAM之间以及闪速存储器和缓冲RAM之间的数据传输，因此， 同时执行缓冲RAM和外部主机之间的数据传输。 并且与执行缓冲RAM和闪速存储器之间的数据传输并行。

公开(公告)号：US06266279B1

公开(公告)日：2001-07-24

申请号：US09621356

申请日：2000-07-21

Applicant: Yoshimasa Yoshimura

Inventor： Yoshimasa Yoshimura

IPC: G11C1600

CPC classification number: G11C16/26 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10

Abstract: An object is to obtain a nonvolatile semiconductor memory device which can achieve a reduction in processing time required for data writing operation and an increase in storage density through the use of multi-valued MOS transistors. In operation for writing data into cells, the amount of charge injected into the floating gates is controlled so as to set the threshold voltages of the MOS transistors at all different values. When reading data from the cells, the data is read by determining whether the threshold voltages of the MOS transistors are higher or lower relative to each other.

Abstract translation: 本发明的目的是获得一种通过使用多值MOS晶体管可以实现数据写入操作所需的处理时间的减少和存储密度的增加的非易失性半导体存储器件。 在将数据写入单元中的操作中，控制注入到浮置栅极的电荷量，以将MOS晶体管的阈值电压设置在所有不同的值。 当从单元读取数据时，通过确定MOS晶体管的阈值电压是否相对于彼此更高或更低来读取数据。

公开(公告)号：US5950013A

公开(公告)日：1999-09-07

申请号：US908596

申请日：1997-08-08

Applicant: Yoshimasa Yoshimura ,  Masanori Takao

Inventor： Yoshimasa Yoshimura ,  Masanori Takao

IPC: G06F1/26 ,  G06F1/28 ,  G06F1/30 ,  G06F9/24 ,  G06F9/445 ,  G06F12/16 ,  G06K17/00 ,  G06F15/00

CPC classification number: G06F9/4401 ,  G06F9/24

Abstract: A memory card consisting of volatile memory that is used connected to a host system apparatus and operated by a power supplied from said host system apparatus, comprises a main memory consisting of volatile memory and a submemory consisting of flash memory wherein when the power is tuned off, the host system apparatus copies data stored in the main memory into the submemory at addresses, corresponding to addresses of the main memory, and when the power is turned on, the host system apparatus writes data stored in the submemory into the main memory at the original addresses.

Abstract translation: 由易失性存储器组成的存储卡，其被连接到主机系统装置并由所述主机系统装置提供的电力操作，包括由易失性存储器和由闪存组成的子存储器组成的主存储器，其中当电源被关闭时 主机系统装置将存储在主存储器中的数据以对应于主存储器的地址的地址复制到子存储器中，并且当电源接通时，主机系统装置将存储在子存储器中的数据写入主存储器 原始地址

公开(公告)号：US5917467A

公开(公告)日：1999-06-29

申请号：US663845

申请日：1996-06-14

Applicant: Yoshimasa Yoshimura

Inventor： Yoshimasa Yoshimura

IPC: G06F3/147 ,  G09G5/00 ,  H04N5/66

CPC classification number: H04N21/4113 ,  G06F3/147 ,  H04N21/4183 ,  G09G2360/06 ,  G09G5/363 ,  H04N5/4401

Abstract: The objective of the invention is to provide a portable information processing apparatus and a PC card for its expansion that facilitate transient and still images. A PC card system of the invention comprises a PC card capable of processing video signals and an information processing apparatus having a liquid crystal display, PC card slots, a VGA controller that converts pixel data into analog RGB signals, and an LCD controller that controls the liquid crystal display. The information processing apparatus further has an analog RGB signal lines and synchronizing signal lines between the LCD controller and the PC card slots, and a pixel data bus between the VGA controller and the PC card slots.

Abstract translation: 本发明的目的是提供一种便携式信息处理装置和用于其扩展的PC卡，其便于暂时和静止图像。 本发明的PC卡系统包括能够处理视频信号的PC卡和具有液晶显示器的信息处理装置，PC卡插槽，将像素数据转换为模拟RGB信号的VGA控制器，以及控制 液晶显示器。 信息处理装置还具有模拟RGB信号线和LCD控制器与PC卡插槽之间的同步信号线以及VGA控制器和PC卡插槽之间的像素数据总线。

公开(公告)号：US5802328A

公开(公告)日：1998-09-01

申请号：US759000

申请日：1996-12-02

Applicant: Yoshimasa Yoshimura

Inventor： Yoshimasa Yoshimura

IPC: G06K17/00 ,  G06F13/00 ,  G06F13/40 ,  H01R13/64 ,  H05K7/14 ,  H01R9/09 ,  H01R13/642 ,  H05K7/10

CPC classification number: H05K7/1455 ,  G06F13/4081 ,  H05K7/1459 ,  Y02B60/1228 ,  Y02B60/1235

Abstract: The PC card system device including a PC card in conformity with the PC card standard and an information processing device which the PC card is to be connected, comprises a card connector provided in the PC card, a device connector, provided in the information processing device, a connection state detector for detecting the connection state of the PC card according to the signal level of at least one contact of the device connector, and an interface controller for controlling the signal transfer from the device connector according to the determination of the connection state detector. The interface controller prohibits any signal transfer from the device connector if the connection state detector determines that the PC card is incorrectly connected to the information processing device.

Abstract translation: 包括符合PC卡标准的PC卡和PC卡要连接的信息处理设备的PC卡系统设备包括设置在PC卡中的卡连接器，设置在信息处理设备中的设备连接器 ，连接状态检测器，用于根据设备连接器的至少一个触点的信号电平检测PC卡的连接状态;以及接口控制器，用于根据连接状态的确定来控制来自设备连接器的信号传送 探测器。 如果连接状态检测器确定PC卡不正确地连接到信息处理设备，则接口控制器禁止从设备连接器传送任何信号。

公开(公告)号：US5394300A

公开(公告)日：1995-02-28

申请号：US002807

申请日：1993-01-11

Applicant: Yoshimasa Yoshimura

Inventor： Yoshimasa Yoshimura

IPC: B42D15/10 ,  G06K19/077 ,  H01R12/71 ,  H05K1/14 ,  H05K1/18 ,  H05K3/34 ,  H05K3/36

CPC classification number: G06K19/077 ,  H05K1/141 ,  H05K1/181 ,  H05K1/182 ,  H05K2201/09072 ,  H05K2201/10159 ,  H05K2201/10689 ,  H05K2201/10757 ,  H05K2201/10946 ,  H05K2203/1572 ,  H05K3/3421 ,  H05K3/3426 ,  H05K3/368

Abstract: In an IC memory card, sub-modules, in each of which a plurality of memory ICs are mounted on each of two opposed surfaces of a sub-substrate, are mounted on each of two opposed surfaces of a single substrate. Since the number of substrates connected to a connector is one, soldering of the connector is facilitated, and the structure of the connector can be simplified. Furthermore, in an IC memory card, the sub-modules may be mounted on the substrate in such a manner that they are stacked in two stages at an opening in the substrate. In this way, the thickness of the IC memory card can be minimized. Also, the use of the die bonding process makes connection between the sub-module and the substrate easy.

Abstract translation: 在IC存储卡中，在单个基板的两个相对的表面的每一个上安装在每个辅助基板的两个相对的表面中的每一个上安装多个存储器IC的子模块。 由于连接到连接器的基板的数量为一个，所以连接器的焊接变得容易，并且可以简化连接器的结构。 此外，在IC存储卡中，子模块可以以这样的方式安装在基板上，使得它们在基板的开口处分成两层。 以这种方式，可以将IC存储卡的厚度最小化。 此外，使用芯片接合工艺使得子模块和基板之间的连接变得容易。