Method of manufacturing mask
    11.
    发明申请
    Method of manufacturing mask 失效
    制作面膜的方法

    公开(公告)号:US20080097729A1

    公开(公告)日:2008-04-24

    申请号:US11590244

    申请日:2006-10-31

    CPC classification number: G03F1/70 G03F1/36

    Abstract: A method of manufacturing a mask includes designing a second mask data pattern for forming a first mask data pattern, creating a first emulation pattern, which is determined from the second mask data pattern, using a first emulation, creating a second emulation pattern, which is determined from the first emulation pattern, using a second emulation, comparing a pattern, in which the first and second emulation patterns overlap, with the first mask data pattern, and manufacturing a mask layer, which corresponds to the second mask data pattern, according to results of the comparison.

    Abstract translation: 制造掩模的方法包括设计用于形成第一掩模数据图案的第二掩模数据图案,使用第一仿真创建从第二掩模数据图案确定的第一仿真图案,创建第二仿真图案,其是第二仿真模式 根据第一仿真模式确定,使用第二仿真,将第一和第二仿真模式重叠的模式与第一掩模数据模式进行比较,并根据第二掩模数据模式制造对应于第二掩模数据模式的掩模层 比较结果。

    Mask having balance pattern and method of patterning photoresist using the same
    12.
    发明申请
    Mask having balance pattern and method of patterning photoresist using the same 审中-公开
    具有平衡图案的掩模和使用其形成光致抗蚀剂的方法

    公开(公告)号:US20070178391A1

    公开(公告)日:2007-08-02

    申请号:US11525965

    申请日:2006-09-25

    CPC classification number: G03F7/70433 G03F1/36 G03F1/80

    Abstract: A method and mask having balance patterns for reducing and/or preventing chemical flare from occurring in a photoresist between a first mask region and a second mask region. Balance patterns formed on the mask may have a desired and/or predetermined pitch and may be regularly arranged. If the pitch of the balance patterns is equal to or smaller than a threshold value, the balance patterns may not allow the patterns to be transferred onto a photoresist. In addition, the photoresist corresponding to the balance patterns may be either completely removed or completely remain depending on the duty of the balance patterns.

    Abstract translation: 一种具有用于减少和/或防止在第一掩模区域和第二掩模区域之间的光致抗蚀剂中发生化学闪光的平衡图案的方法和掩模。 形成在掩模上的平衡图案可以具有期望的和/或预定的间距,并且可以规则地布置。 如果平衡图案的间距等于或小于阈值,则平衡图案可能不允许将图案转印到光致抗蚀剂上。 此外,根据平衡图案的占空比,对应于平衡图案的光致抗蚀剂可以完全去除或完全保留。

    Recombinant GRAS strains expressing thermophilic arabinose isomerase as an active form and method of preparing food grade tagatose by using the same
    16.
    发明授权
    Recombinant GRAS strains expressing thermophilic arabinose isomerase as an active form and method of preparing food grade tagatose by using the same 有权
    表达嗜热阿拉伯糖异构酶作为活性形式的重组GRAS菌株和使用其制备食品级塔格糖的方法

    公开(公告)号:US08137946B2

    公开(公告)日:2012-03-20

    申请号:US12506581

    申请日:2009-07-21

    CPC classification number: C12N9/90 C12P19/24

    Abstract: The present invention relates to a recombinant GRAS (Generally Recognized As Safe) strains expressing thermophilic arabinose isomerase as an active form and method of food grade tagatose by using the same, and more precisely, a gene encoding arabinose isomerase originating from the thermophilic Geobacillus stearothermophilus DSM22 and Geobacillus thermodenitrificans, a recombinant expression vector containing the gene, a recombinant GRAS strains expressing the thermophilic arabinose isomerase as an active form by transformed with the expression vector, and a method of preparing food grade tagatose from galactose by using the same.

    Abstract translation: 本发明涉及一种表达嗜热阿拉伯糖异构酶的重组GRAS(一般被认为是安全的)菌株,作为食物级塔格糖的活性形式和方法,更确切地说,是编码源自嗜热嗜热脂肪芽孢杆菌DSM22的阿拉伯糖异构酶的基因 和热过氧亚硝酸芽孢杆菌,含有该基因的重组表达载体,通过用表达载体转化表达嗜热阿拉伯糖异构酶作为活性形式的重组GRAS菌株,以及通过使用其从半乳糖制备食品级塔格糖的方法。

    BOARD ON CHIP PACKAGE SUBSTRATE AND MANUFACTURING METHOD THEREOF
    17.
    发明申请
    BOARD ON CHIP PACKAGE SUBSTRATE AND MANUFACTURING METHOD THEREOF 审中-公开
    芯片包装基板及其制造方法

    公开(公告)号:US20110101510A1

    公开(公告)日:2011-05-05

    申请号:US12912202

    申请日:2010-10-26

    Abstract: A single-layer board on chip package substrate and a manufacturing method thereof are disclosed. In accordance with an embodiment of the present invention, the substrate includes an insulator, a first pad and a second pad, which are provided on an upper surface of the insulator, a through-hole, which is formed in the insulator such that a lower surface of the first pad is exposed, and a solder resist layer, which is formed on the upper surface of the insulator such that at least a portion of the second pad is exposed.

    Abstract translation: 公开了一种单层片上封装衬底及其制造方法。 根据本发明的实施例,基板包括设置在绝缘体的上表面上的绝缘体,第一焊盘和第二焊盘,形成在绝缘体中的通孔使得下部 暴露第一焊盘的表面和形成在绝缘体的上表面上的阻焊层,使得第二焊盘的至少一部分露出。

    Methods for forming fine pattern of semiconductor device
    18.
    发明授权
    Methods for forming fine pattern of semiconductor device 有权
    用于形成半导体器件精细图案的方法

    公开(公告)号:US07172974B2

    公开(公告)日:2007-02-06

    申请号:US10462448

    申请日:2003-06-16

    CPC classification number: G03F7/40 H01L21/0275 H01L21/0276

    Abstract: Provided is a method for forming a fine pattern of a semiconductor device by controlling the amount of flow of a resist pattern, including forming a resist pattern having a predetermined pattern distance on a material layer to be etched, forming a flow control barrier layer on the resist pattern to control the amount of flow during a subsequent resist flow process and to make the profile of the flowed pattern be vertical, optionally forming the flow control barrier layer by coating a material including a water-soluble high-molecular material and a crosslinking agent on the resist pattern, mixing and baking the coated material layer, and processing the resultant structure using deionized water, carrying out the flow resist process to form a hyperfine pattern and etching the lower material layer, and thereby forming fine patterns having the shape of contact holes or lines and spaces to have a critical dimension of about 100 nm or less, even with use of a KrF resist.

    Abstract translation: 提供了一种通过控制抗蚀剂图案的流动量来形成半导体器件的精细图案的方法,包括在待蚀刻的材料层上形成具有预定图案距离的抗蚀剂图案,在其上形成流动控制阻挡层 抗蚀剂图案以控制随后的抗蚀剂流动过程期间的流量并使流动图案的轮廓垂直,任选地通过涂覆包括水溶性高分子材料和交联剂的材料形成流动控制阻挡层 在抗蚀剂图案上,混合和烘烤涂覆材料层,并使用去离子水处理所得到的结构,进行流动阻挡工艺以形成超精细图案并蚀刻下部材料层,从而形成具有接触形状的精细图案 空穴或线和空间具有约100nm或更小的临界尺寸,即使使用KrF抗蚀剂。

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