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    Method for forming an improved low power SRAM contact
    12.
    发明申请
    Method for forming an improved low power SRAM contact 失效
    形成改进的低功率SRAM触点的方法

    公开(公告)号：US20070205414A1

    公开(公告)日：2007-09-06

    申请号：US11800503

    申请日：2007-05-07

    Applicant: Chia-Der Chang ,  Yu-Ching Chang ,  Chien-Chih Chou ,  Yi-Tung Yen

    Inventor： Chia-Der Chang ,  Yu-Ching Chang ,  Chien-Chih Chou ,  Yi-Tung Yen

    IPC: H01L27/108

    CPC classification number: H01L21/31116 ,  H01L21/0276 ,  H01L27/11 ,  H01L27/1104

    Abstract: A method of forming contact openings in a semiconductor device including providing a semiconducting substrate; forming an etch stop layer on said semiconducting substrate; forming a dielectric layer on said etch stop layer; forming a bottom anti-reflective coating (BARC) on said dielectric layer; forming and patterning a mask on said BARC layer; and, forming at least a first contact opening exposing said etch stop layer by a first etching process.

    Abstract translation: 一种在半导体器件中形成接触开口的方法，包括提供半导体衬底; 在所述半导体衬底上形成蚀刻停止层; 在所述蚀刻停止层上形成介电层; 在所述介​​电层上形成底部抗反射涂层（BARC）; 在所述BARC层上形成和图案化掩模; 并且形成至少第一接触开口，通过第一蚀刻工艺暴露所述蚀刻停止层。

    IMAGING SYSTEM AND IMAGE PROCESSING METHOD THEREOF
    15.
    发明申请
    IMAGING SYSTEM AND IMAGE PROCESSING METHOD THEREOF 有权
    成像系统及其图像处理方法

    公开(公告)号：US20130163840A1

    公开(公告)日：2013-06-27

    申请号：US13558362

    申请日：2012-07-26

    Applicant: Arvin Huang-Te Li ,  Yio-Wha Shau ,  Yu-Ching Chang ,  Bai-Kuang Hwang

    Inventor： Arvin Huang-Te Li ,  Yio-Wha Shau ,  Yu-Ching Chang ,  Bai-Kuang Hwang

    IPC: G06K9/46

    CPC classification number: A61B8/5207 ,  A61B8/08 ,  A61B8/461 ,  A61B8/5215

    Abstract: An image processing method is provided. The image processing method includes the following steps. A plurality of raw signal is received by a signal transceiving module of the ultrasound imaging system. It is determined whether each of the raw signals satisfies any condition in a condition group, and the raw signal satisfying any condition in the condition group is mapped to one of a plurality of preset constants to generate a plurality of first data. The raw signals not satisfying any condition in the condition group are processed according to a calculation formula to generate a plurality of second data. A beamforming procedure is simultaneously performed on the first and second data to obtain a beamformed image. The beamformed image is transformed to obtain an image of a region to be detected. Furthermore, an imaging system using the foregoing image processing method is also provided.

    Abstract translation: 提供了图像处理方法。 图像处理方法包括以下步骤。 多个原始信号由超声波成像系统的信号收发模块接收。 确定每个原始信号是否满足条件组中的任何条件，并且满足条件组中的任何条件的原始信号被映射到多个预设常数中的一个以产生多个第一数据。 根据计算公式处理条件组中不满足任何条件的原始信号，以生成多个第二数据。 对第一和​​第二数据同时执行波束形成过程以获得波束形成的图像。 波束形成的图像被变换以获得要检测的区域的图像。 此外，还提供了使用上述图像处理方法的成像系统。

    WAFER SPLITTING APPARATUS AND WAFER SPLITTING PROCESS
    16.
    发明申请
    WAFER SPLITTING APPARATUS AND WAFER SPLITTING PROCESS 审中-公开
    WAFER分割设备和WAFER分割过程

    公开(公告)号：US20120160227A1

    公开(公告)日：2012-06-28

    申请号：US13043476

    申请日：2011-03-09

    Applicant: Chien-Sen Weng ,  Meng-Yeng Xing ,  Wei-Chang Yu ,  Chih-Sheng Chen ,  Yu-Ching Chang

    Inventor： Chien-Sen Weng ,  Meng-Yeng Xing ,  Wei-Chang Yu ,  Chih-Sheng Chen ,  Yu-Ching Chang

    IPC: B28D5/04

    CPC classification number: B28D5/0041 ,  B28D5/0023 ,  H01L33/0095

    Abstract: A wafer splitting apparatus suitable for splitting a plurality of chip regions of a wafer into a plurality of independent dice is provided. The wafer splitting apparatus includes a splitting knife body and at least a vibrating hammer. The splitting knife body is disposed at one side of the wafer, and has a first surface facing the wafer. The first surface stretches over a plurality of chip regions in all extending directions of the first surface passing through a center of the first surface. The splitting knife body is disposed between the wafer and the vibrating hammer, and the vibrating hammer is suitable for knocking the splitting knife body in a direction toward the wafer to make the splitting knife body move toward the wafer, so as to split the chip regions of the wafer into a plurality of independent dice. A wafer splitting process is also provided.

    Abstract translation: 提供了一种适于将晶片的多个芯片区域分成多个独立裸片的晶片分割装置。 晶片分割装置包括分割刀体和至少一个振动锤。 分割刀体设置在晶片的一侧，并且具有面向晶片的第一表面。 第一表面在通过第一表面的中心的第一表面的所有延伸方向上在多个芯片区域上延伸。 分割刀体设置在晶片和振动锤之间，振动锤适用于朝向晶片的方向敲击分割刀体，使分割刀体朝向晶片移动，从而将芯片区域 的晶片进入多个独立的骰子。 还提供了晶圆分离工艺。

    Protection circuit
    18.
    发明申请
    Protection circuit 失效
    保护电路

    公开(公告)号：US20060164768A1

    公开(公告)日：2006-07-27

    申请号：US11334412

    申请日：2006-01-19

    Applicant: Yu-Ching Chang ,  Ming-Chia Wu ,  Chung-Jung Kuo

    Inventor： Yu-Ching Chang ,  Ming-Chia Wu ,  Chung-Jung Kuo

    IPC: H02H7/04

    CPC classification number: H02H3/20 ,  H02H3/066

    Abstract: A protection circuit is coupled between a secondary winding of a transformer and a load. When voltage at the secondary winding of the transformer becomes abnormal, the protection circuit disconnects the power connection to the load so as to protect the load from damage. When the voltage at the secondary winding of the transformer returns normal, the protection circuit restores power to the load.

    Abstract translation: 保护电路耦合在变压器的次级绕组和负载之间。 当变压器次级绕组的电压异常时，保护电路断开与负载的电源连接，以保护负载免受损坏。 当变压器次级绕组的电压恢复正常时，保护电路恢复负载的电力。

    Tungsten plug with conductor capping layer
    19.
    发明授权
    Tungsten plug with conductor capping layer 有权
    钨丝塞带导体盖层

    公开(公告)号：US06835649B2

    公开(公告)日：2004-12-28

    申请号：US10161570

    申请日：2002-06-03

    Applicant: Wei-Cheng Lee ,  Wen-Chen Chien ,  Yu-Da Fan ,  Kuo-Yen Liu ,  Yu-Ching Chang

    Inventor： Wei-Cheng Lee ,  Wen-Chen Chien ,  Yu-Da Fan ,  Kuo-Yen Liu ,  Yu-Ching Chang

    IPC: H01L214763

    CPC classification number: H01L21/76877

    Abstract: Within a method for forming a microelectronic fabrication there is provided a substrate having formed thereover a patterned dielectric layer which defines a via. There is also formed within a lower portion of the via a tungsten stud layer having a recess thereabove within the via. There is also formed within the recess a patterned conductor capping layer formed of a conductor material other than tungsten. The patterned conductor capping layer may seal a void formed within the tungsten stud layer.

    Abstract translation: 在用于形成微电子制造的方法中，提供了在其上形成限定通孔的图案化电介质层的衬底。 在通孔的下部还形成有在其内部具有通孔内的凹部的钨螺柱层。 在凹部内还形成有由钨以外的导体材料形成的图案化导体封盖层。 图案化的导体封盖层可以密封形成在钨钉层内的空隙。

    Low stress integrated circuit fusible link
    20.
    发明授权
    Low stress integrated circuit fusible link 失效
    低应力集成电路熔断连接

    公开(公告)号：US06734525B2

    公开(公告)日：2004-05-11

    申请号：US10144014

    申请日：2002-05-13

    Applicant: Chieh-Chih Chou ,  Jiun-Pyng You ,  Yu-Ching Chang

    Inventor： Chieh-Chih Chou ,  Jiun-Pyng You ,  Yu-Ching Chang

    IPC: H01L2900

    CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A fuse structure and method for fabricating same are disclosed. The fuse structure is designed for opening by conventional laser energy application. The fuse structure is characterized by an absence of high stress areas in the surrounding substrate thereby resulting in higher fabrication yields due to lower occurrence of substrate fracturing or other damage occasioned by the opening of the fuse.

    Abstract translation: 公开了一种熔丝结构及其制造方法。 保险丝结构设计用于通过常规激光能量打开。 熔丝结构的特征在于在周围基板中不存在高应力区域，由此导致更高的制造成本，这是由于基板断裂的较少发生或由熔断器的开启引起的其它损坏。

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