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11.发明公开公开(公告)号：US20230396240A1
公开(公告)日：2023-12-07
申请号：US17831013
申请日：2022-06-02
Applicant: Advanced Micro Devices, Inc.
Inventor： Thomas H. Likens , Gerald R. Talbot
CPC classification number: H03K3/0322 , G06F1/06
Abstract: A three-stage differential ring oscillator circuit has a first differential stage, a second differential stage, and a third differential stage and generates six phases (two in each stage) used to form differential in-phase and quadrature-phase clock signals. A cross coupled inverter pair couples the first stage output signals. A second cross coupled inverter pair couples the second stage output signals. A third cross coupled inverter pair couples the third stage output signals. A first interpolator generates a first quadrature-phase clock signal using two phases (one from the positive portion of the second stage and one from the negative portion of the third stage) and a second interpolator generates a second quadrature-phase clock signal using two phases (one from the negative portion of the second stage and one from the positive portion of the third stage). Two phases from the first differential stage form the differential pair of in-phase clock signals.
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公开(公告)号：US20200344039A1
公开(公告)日：2020-10-29
申请号：US16709472
申请日：2019-12-10
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Varun Gupta , Milam Paraschou , Gerald R. Talbot , Gurunath Dollin , Damon Tohidi , Eric Ian Carpenter , Chad S. Gallun , Jeffrey Cooper , Hanwoo Cho , Thomas H. Likens, III , Scott F. Dow , Michael J. Tresidder
Abstract: Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.
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13.发明申请公开(公告)号：US20180054223A1
公开(公告)日：2018-02-22
申请号：US15240549
申请日：2016-08-18
Applicant: Advanced Micro Devices, Inc.
Inventor： Milam Paraschou , Gerald R. Talbot , Dean E. Gonzales
CPC classification number: H04B1/0475 , H03F3/45475 , H03F2200/369 , H03F2203/45034 , H03F2203/45134 , H03F2203/45138 , H03H11/52
Abstract: Systems, apparatuses, and methods for implementing a negative resistance circuit for bandwidth extension are disclosed. Within a feedback path of a differential signal path, capacitors are placed on the inputs and outputs of a fully differential amplifier connecting to the differential signal path. In one embodiment, a circuit includes a fully differential amplifier and four capacitors. A first capacitor is coupled between a first signal path and a non-inverting input terminal of the amplifier and a second capacitor is coupled between the first signal path and a non-inverting output terminal of the amplifier. A third capacitor is coupled between a second signal path and an inverting input terminal of the amplifier and a fourth capacitor is coupled between the second signal path and an inverting output terminal of the amplifier. The first and second signal paths carry a differential signal.
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14.发明授权Selective insertion of clock mismatch compensation symbols in signal transmissions based on a receiver's compensation capability 有权基于接收机的补偿能力，在信号传输中选择性地插入时钟失配补偿符号公开(公告)号：US09213355B2
公开(公告)日：2015-12-15
申请号：US13670086
申请日：2012-11-06
Applicant: Advanced Micro Devices, Inc.
Inventor： Gordon F. Caruk , Gerald R. Talbot
Abstract: In a system comprising a first device and a second device coupled via an interconnect, a method includes setting a rate of insertion of clock mismatch compensation symbols for a transmit port of the first device to one of a plurality of rates of insertion responsive to the second device having capability to compensate for a clock frequency mismatch. A device includes an interconnect interface comprising a transmit port and a receive port, and a configuration structure. The configuration structure comprises a capability field to store a value indicating whether the device has a capability to compensate for a clock frequency mismatch, and an enable field. The device further includes a packet control module to configure a rate of insertion of clock mismatch compensation symbols by the transmit port into a data stream responsive to a value stored at the enable field.
Abstract translation: 在包括通过互连耦合的第一设备和第二设备的系统中，一种方法包括将响应于第二设备的多个插入速率的第一设备的发送端口的时钟失配补偿符号的插入速率设置为 器件具有补偿时钟频率不匹配的能力。 一种设备包括包括发送端口和接收端口的互连接口以及配置结构。 配置结构包括存储指示设备是否具有补偿时钟频率失配的能力的值的能力字段和启用字段。 该设备还包括分组控制模块，用于响应于存储在启用字段的值，将发送端口的时钟失配补偿符号的速率配置成数据流。
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15.发明申请METHOD AND APPARATUS FOR POWER-UP DETECTION FOR AN ELECTRICAL MONITORING CIRCUIT 有权用于电力监测电路上电检测的方法和装置公开(公告)号：US20150130519A1
公开(公告)日：2015-05-14
申请号：US14518591
申请日：2014-10-20
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Brian W. Amick , Gerald R. Talbot , Warren Anderson
IPC: H03K3/01
CPC classification number: H03K17/22
Abstract: A method and apparatus is provided for outputting a reset signal during power-up until two conditions are satisfied. In one embodiment, the method and apparatus includes a voltage detector that provides a first output (“VO1”) when an output voltage of a regulator (“VREG”) exceeds a threshold voltage, thereby satisfying a first condition, a comparator receiving a first input voltage and a second input voltage, the comparator providing a second output (“VO2”) when the first input voltage exceeds the second input voltage, thereby satisfying a second condition, and a release circuit that outputs the reset signal unless the voltage detector provides VO1 while the comparator provides VO2.
Abstract translation: 提供一种方法和装置，用于在上电期间输出复位信号，直到满足两个条件。 在一个实施例中，所述方法和装置包括电压检测器，当调节器的输出电压（“VREG”）超过阈值电压时提供第一输出（“VO1”），从而满足第一条件，比较器接收第一 输入电压和第二输入电压，当第一输入电压超过第二输入电压时，比较器提供第二输出（“VO2”），从而满足第二条件，以及释放电路，输出复位信号，除非电压检测器提供 VO1，而比较器提供VO2。
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Patent Agency Ranking
公开(公告)号：US12034440B2
公开(公告)日：2024-07-09
申请号：US17566199
申请日：2021-12-30
Applicant: Advanced Micro Devices, Inc.
Inventor： Rajesh Kumar , Edoardo Prete , Gerald R. Talbot , Ethan Crain , Tracy J. Feist , Jeffrey Cooper
IPC: H03K19/01 , H03K19/0175 , H03F3/45
CPC classification number: H03K19/017509 , H03F3/45475
Abstract: Systems, apparatuses, and methods for implementing a combo scheme for direct current (DC) level shifting of signals are disclosed. A receiver circuit receives an input signal on a first interface. The first interface is coupled to a resistor in parallel with a capacitor which passes the input signal to a second interface. Also, the first interface is coupled to a first pair of current sources between ground and a voltage source, and the second interface is coupled to a second pair of current sources between ground and the voltage source. An op-amp drives the current sources based on a difference between a sensed common mode voltage and a reference voltage. Based on this circuit configuration, the receiver circuit is able to prevent baseline wander, perform a DC level shift of the input signal, and achieve linear equalization of the input signal.
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公开(公告)号：US20230305979A1
公开(公告)日：2023-09-28
申请号：US17705048
申请日：2022-03-25
Applicant: Advanced Micro Devices, Inc.
Inventor： Gurunath Dollin , Edoardo Prete , Milam Paraschou , Edward Wade Thoenes , Ryan J. Hensley , Gerald R. Talbot
IPC: G06F13/40 , G06F13/42 , G06F1/12 , G06F1/08 , H03K19/173
CPC classification number: G06F13/4022 , G06F13/4282 , G06F13/4068 , G06F1/12 , G06F1/08 , H03K19/1737
Abstract: Systems, apparatuses, and methods for implementing a periodic receiver clock data recovery scheme with dynamic data edge paths are disclosed. An IQ link calibration scheme performs a non-destructive data and edge path switch to determine an IQ offset without disturbing the data. A data path and an edge path pass through multiple stages of deserializers to widen the data path, with the deserializers clocked by clock divided versions of the original data and edge clocks. To initiate a calibration routine, the edge clock is aligned with the data clock, and then data and edge paths are swapped at a common point in a slower clock domain. The data path is then calibrated while the edge path carries the data signal. After the data path is calibrated, the edge and data paths are swapped back to the original configuration.
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公开(公告)号：US11283589B2
公开(公告)日：2022-03-22
申请号：US17128720
申请日：2020-12-21
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Varun Gupta , Milam Paraschou , Gerald R. Talbot , Gurunath Dollin , Damon Tohidi , Eric Ian Carpenter , Chad S. Gallun , Jeffrey Cooper , Hanwoo Cho , Thomas H. Likens, III , Scott F. Dow , Michael J. Tresidder
Abstract: Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.
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公开(公告)号：US20210028995A1
公开(公告)日：2021-01-28
申请号：US16993678
申请日：2020-08-14
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Stanley Ames Lackey, JR. , Damon Tohidi , Gerald R. Talbot , Edoardo Prete
Abstract: Systems, apparatuses, and methods for utilizing training sequences on a replica lane are described. A transmitter is coupled to a receiver via a communication channel with a plurality of lanes. One of the lanes is a replica lane used for tracking the drift in the optimal sampling point due to temperature variations, power supply variations, or other factors. While data is sent on the data lanes, test patterns are sent on the replica lane to determine if the optimal sampling point for the replica lane has drifted since a previous test. If the optimal sampling point has drifted for the replica lane, adjustments are made to the sampling point of the replica lane and to the sampling points of the data lanes.
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公开(公告)号：US10749756B2
公开(公告)日：2020-08-18
申请号：US15192287
申请日：2016-06-24
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Stanley Ames Lackey, Jr. , Damon Tohidi , Gerald R. Talbot , Edoardo Prete
Abstract: Systems, apparatuses, and methods for utilizing training sequences on a replica lane are described. A transmitter is coupled to a receiver via a communication channel with a plurality of lanes. One of the lanes is a replica lane used for tracking the drift in the optimal sampling point due to temperature variations, power supply variations, or other factors. While data is sent on the data lanes, test patterns are sent on the replica lane to determine if the optimal sampling point for the replica lane has drifted since a previous test. If the optimal sampling point has drifted for the replica lane, adjustments are made to the sampling point of the replica lane and to the sampling points of the data lanes.
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