公开(公告)号：US20220328354A1

公开(公告)日：2022-10-13

申请号：US17847419

申请日：2022-06-23

Applicant: Applied Materials, Inc.

Inventor： Peng SUO ,  Ying W. WANG ,  Guan Huei SEE ,  Chang Bum YONG ,  Arvind SUNDARRAJAN

IPC: H01L21/768 ,  H01L21/308 ,  H01L21/288 ,  H01L21/285 ,  H01L21/306

Abstract: The present disclosure relates to through-via structures with dielectric shielding of interconnections for advanced wafer level semiconductor packaging. The methods described herein enable the formation of high thickness dielectric shielding layers within low aspect ratio through-via structures, thus facilitating thin and small-form-factor package structures having high I/O density with improved bandwidth and power.

公开(公告)号：US20220181142A1

公开(公告)日：2022-06-09

申请号：US17110940

申请日：2020-12-03

Applicant: APPLIED MATERIALS, INC.

Inventor： Chien-Kang HSIUNG ,  James S. PAPANU ,  Arvind SUNDARRAJAN

IPC: H01L21/02 ,  H01L21/67 ,  H01L21/683 ,  H01L21/687

Abstract: Methods and apparatus for far edge trimming are provided herein. For example, an apparatus includes an integrated tool for processing a silicon substrate, comprising a vacuum substrate transfer chamber, an edge trimming apparatus coupled to the vacuum substrate transfer chamber and comprising a high pulse frequency laser and substrate support, wherein at least one of the high pulse frequency laser or the substrate support are movable with respect to each other and configured to trim about 2 mm to about 5 mm from a peripheral edge of a substrate when disposed on the substrate support, and a plasma etching apparatus coupled to the vacuum substrate transfer chamber and configured to etch silicon.

公开(公告)号：US20210035795A1

公开(公告)日：2021-02-04

申请号：US16936918

申请日：2020-07-23

Applicant: APPLIED MATERIALS, INC.

Inventor： Qi Jie PENG ,  Prayudi LIANTO ,  Chin Wei TAN ,  Sriskantharajah THIRUNAVUKARASU ,  Arvind SUNDARRAJAN ,  Jun-Liang SU ,  Fang Jie LIM ,  Manorajh ARUNAKIRI ,  Wei Jie Dickson TEO ,  Karrthik PARATHITHASAN ,  Puay Han TAN

IPC: H01L21/02 ,  H01L21/683 ,  H01L21/324

Abstract: Methods and apparatus for reducing warpage of a substrate. In some embodiments, a method of reducing substrate warpage comprises heating the substrate with an epoxy layer to at least a glass transition temperature of the epoxy layer while allowing the substrate to expand; maintaining the at least the glass transition temperature of the substrate until the substrate is constrained; constraining the substrate with a total clamping force of approximately 5000N to approximately 7000N exerted towards the substrate from a top direction and a bottom direction; applying at least one electrostatic field to the substrate with a first electrostatic chuck positioned above the substrate and a second electrostatic chuck positioned below the substrate; and rapidly cooling the substrate using a first liquid convection heat sink positioned above the substrate and a second liquid convection heat sink positioned below the substrate.

公开(公告)号：US20180374718A1

公开(公告)日：2018-12-27

申请号：US15840900

申请日：2017-12-13

Applicant: Applied Materials, Inc.

Inventor： Han-Wen CHEN ,  Steven VERHAVERBEKE ,  Roman GOUK ,  Guan Huei SEE ,  Yu GU ,  Arvind SUNDARRAJAN ,  Kyuil CHO ,  Colin Costano NEIKIRK ,  Boyi FU

IPC: H01L21/56 ,  H01L23/31

Abstract: Embodiments of the present disclosure generally describe methods for minimizing the occurrence and the extent of die shift during the formation of a reconstituted substrate in fan-out wafer level packaging processes. Die shift is a process defect that occurs when a die (device) moves from its intended position within a reconstituted substrate during the formation thereof. Generally, the methods disclosed herein include depositing a device immobilization layer and/or a plurality of device immobilization beads over and/or adjacent to a plurality of singular devices (individual dies), and the carrier substrate they are positioned on, before forming a reconstituted substrate with an epoxy molding compound. The device immobilization layer and/or the plurality of device immobilization beads immobilize the plurality of singular devices and prevents them from shifting on the carrier substrate during the molding process.

公开(公告)号：US20180281151A1

公开(公告)日：2018-10-04

申请号：US15474736

申请日：2017-03-30

Applicant: Applied Materials, Inc.

Inventor： Seshadri RAMASWAMI ,  Rajeev BAJAJ ,  Niranjan KUMAR ,  Sriskantharajah THIRUNAVUKARASU ,  Arvind SUNDARRAJAN

IPC: B24B37/32 ,  B24B37/20 ,  B24B41/06

Abstract: Embodiments of the disclosure relate to a system, apparatus and method for polishing thin substrates with high planarity. The apparatus comprises a chemical mechanical polishing head and a plate. The polishing head comprises a bottom surface, a retaining ring, a workpiece-receiving pocket defined between the bottom surface and the retaining ring, and at least one vacuum port adapted to provide a vacuum to the workpiece-receiving pocket through the bottom surface of the polishing head. The plate is disposed in the workpiece-receiving pocket such that the upper side of the plate faces the bottom surface of the polishing head and the lower side of the plate faces away from the bottom surface of the polishing head. The plate has a geometry or a material property configured to allow fluid to pass between the upper side and the lower side of the plate upon application of vacuum in the workpiece-receiving pocket.

公开(公告)号：US20240087958A1

公开(公告)日：2024-03-14

申请号：US18508801

申请日：2023-11-14

Applicant: Applied Materials, Inc.

Inventor： Peng SUO ,  Ying W. WANG ,  Guan Huei SEE ,  Chang Bum YONG ,  Arvind SUNDARRAJAN

IPC: H01L21/768 ,  H01L21/285 ,  H01L21/288 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L21/76898 ,  H01L21/2855 ,  H01L21/288 ,  H01L21/30625 ,  H01L21/308

Abstract: The present disclosure relates to through-via structures with dielectric shielding of interconnections for advanced wafer level semiconductor packaging. The methods described herein enable the formation of high thickness dielectric shielding layers within low aspect ratio through-via structures, thus facilitating thin and small-form-factor package structures having high I/O density with improved bandwidth and power.

公开(公告)号：US20220165621A1

公开(公告)日：2022-05-26

申请号：US16953869

申请日：2020-11-20

Applicant: Applied Materials, Inc.

Inventor： Peng SUO ,  Ying W. WANG ,  Guan Huei SEE ,  Chang Bum YONG ,  Arvind SUNDARRAJAN

IPC: H01L21/768 ,  H01L21/308 ,  H01L21/306 ,  H01L21/285 ,  H01L21/288

Abstract: The present disclosure relates to through-via structures with dielectric shielding of interconnections for advanced wafer level semiconductor packaging. The methods described herein enable the formation of high thickness dielectric shielding layers within low aspect ratio through-via structures, thus facilitating thin and small-form-factor package structures having high I/O density with improved bandwidth and power.

公开(公告)号：US20220037216A1

公开(公告)日：2022-02-03

申请号：US16944285

申请日：2020-07-31

Applicant: APPLIED MATERIALS, INC.

Inventor： Prayudi LIANTO ,  Sik Hin CHI ,  Shih-Chao HUNG ,  Pin Gian GAN ,  Ricardo Fujii VINLUAN ,  Gaurav MEHTA ,  Ramesh CHIDAMBARAM ,  Guan Huei SEE ,  Arvind SUNDARRAJAN ,  Upendra V. UMMETHALA ,  Wei Hao KEW ,  Muhammad Adli Danish Bin ABDULLAH ,  Michael Charles KUTNEY ,  Mark McTaggart WYLIE ,  Amulya Ligorio ATHAYDE ,  Glen T. MORI

IPC: H01L21/66 ,  H01L21/768 ,  H01L21/304 ,  H01L21/306 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/683

Abstract: Methods and apparatus perform backside via reveal processes using a centralized control framework for multiple process tools. In some embodiments, a method for performing a backside via reveal process may include receiving process tool operational parameters from process tools involved in the backside via reveal process by a central controller, receiving sensor metrology data from at least one or more of the process tools involved in the backside via reveal process, and altering the backside reveal process based, at least in part, on the process tool operational parameters and the sensor metrology data by adjusting two or more of the process tools involved in the backside via reveal process. The profile parameters are configured to prevent backside via breakage during a chemical mechanical polishing (CMP) process.

公开(公告)号：US20190181019A1

公开(公告)日：2019-06-13

申请号：US16276866

申请日：2019-02-15

Applicant: Applied Materials, Inc.

Inventor： Han-Wen CHEN ,  Steven VERHAVERBEKE ,  Roman GOUK ,  Guan Huei SEE ,  Yu GU ,  Arvind SUNDARRAJAN ,  Kyuil CHO ,  Colin Costano NEIKIRK ,  Boyi FU

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L23/13 ,  H01L23/00 ,  H01L21/48 ,  H01L21/311 ,  H01L21/027 ,  H01L21/02 ,  G03F7/00

Abstract: Embodiments of the present disclosure generally describe methods for minimizing the occurrence and the extent of die shift during the formation of a reconstituted substrate in fan-out wafer level packaging processes and reconstituted substrates formed therefrom. Die shift is a process defect that occurs when a die (device) moves from its intended position within a reconstituted substrate during the formation thereof. Generally, the reconstituted substrates disclosed herein include a device immobilization layer and/or a plurality of device immobilization beads over and/or adjacent to a plurality of singular devices (individual dies), and a cured epoxy molding compound formed there over. The device immobilization layer and/or the plurality of device immobilization beads immobilize the plurality of singular devices and prevents them from shifting on the carrier substrate during the molding process.

公开(公告)号：US20180005881A1

公开(公告)日：2018-01-04

申请号：US15200836

申请日：2016-07-01

Applicant: APPLIED MATERIALS, INC.

Inventor： Prayudi LIANTO ,  Sam LEE ,  Charles SHARBONO ,  Marvin Louis BERNT ,  Guan Huei SEE ,  Arvind SUNDARRAJAN

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76879 ,  H01L21/76804 ,  H01L21/76873 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/5329

Abstract: A method of processing a semiconductor substrate includes: immersing a substrate in a first bath, wherein the substrate comprises a barrier layer, a conductive seed layer, and a patterned photoresist layer defining an opening; providing a first electric current between the conductive seed layer and a first anode disposed in electrical contact with the first bath to deposit a conductive material within the opening; stripping the patterned photoresist layer; immersing the substrate in a second bath; providing a second electric current that is a reverse of the first electric current between the conductive seed layer plus the conductive material and a second anode disposed in electrical contact with the second bath; etching the conductive seed layer from atop a field region of the barrier layer; and etching the barrier layer from atop a field region of the substrate.