公开(公告)号：US20250149474A1

公开(公告)日：2025-05-08

申请号：US18809472

申请日：2024-08-20

Applicant: Applied Materials, Inc. ,  Nanyang Technological University

Inventor： Prayudi LIANTO ,  Chuan Seng TAN

IPC: H01L23/00 ,  H01L21/02 ,  H01L21/67 ,  H01L21/762

Abstract: A method for increasing dielectric bonding strength during wafer-level processing is incorporated into a hybrid bonding process. A method may include immersing a substrate into a chemical bath at atmospheric conditions where the chemical bath forms a self-assembled monolayer on metal surfaces of the substrate and selectively depositing a high-k dielectric material to form a dielectric cap on dielectric surfaces of the substrate absent of the self-assembled monolayer.

公开(公告)号：US20240331131A1

公开(公告)日：2024-10-03

申请号：US18128491

申请日：2023-03-30

Applicant: Applied Materials, Inc.

Inventor： Rahul Reddy KOMATIREDDI ,  Rohith CHERIKKALLIL ,  Sneha Rupa KONGARA ,  Satwik Swarup MISHRA ,  Sachin DANGAYACH ,  Si En CHAN ,  Remus Zhen Hui KOH ,  Prayudi LIANTO ,  Yin Wei LIM ,  Peng SUO ,  Krishnaprasad Reddy MALLAVARAM ,  Khor Wui CHENG

IPC: G06T7/00 ,  G06T7/13

CPC classification number: G06T7/001 ,  G06T7/13 ,  G06T2207/20081 ,  G06T2207/20084 ,  G06T2207/30148

Abstract: A method, apparatus and system for the automatic detection and measurement of chipping defects on diced wafers includes receiving an image of at least a portion of a diced wafer, aligning the received image of the at least the portion of the diced wafer, determining edges of the at least the portion of the diced wafer depicted in the aligned, received image, automatically determining at least one baseline from which to measure chipping defects on the at least the portion of the diced wafer from the determined edges, and measuring chipping defects on the at least the portion of the diced wafer using at least one determined, respective baseline. In some embodiments, the method, apparatus and system can further include applying a machine learning model to measured chipping defects to determine if a critical failure exists on the diced wafer.

公开(公告)号：US20240213028A1

公开(公告)日：2024-06-27

申请号：US18086150

申请日：2022-12-21

Applicant: Applied Materials, Inc.

Inventor： Guan Huei SEE ,  ChangBum YONG ,  Prayudi LIANTO ,  Cheng SUN ,  Arvind SUNDARRAJAN

IPC: H01L21/3065

CPC classification number: H01L21/3065

Abstract: A method of thinning a die engaged with a substrate is disclosed, utilizing dry etching of a top surface of the die with a plasma comprising fluorine to selectively remove the top surface of the die relative to a top surface of the substrate.

公开(公告)号：US20210035795A1

公开(公告)日：2021-02-04

申请号：US16936918

申请日：2020-07-23

Applicant: APPLIED MATERIALS, INC.

Inventor： Qi Jie PENG ,  Prayudi LIANTO ,  Chin Wei TAN ,  Sriskantharajah THIRUNAVUKARASU ,  Arvind SUNDARRAJAN ,  Jun-Liang SU ,  Fang Jie LIM ,  Manorajh ARUNAKIRI ,  Wei Jie Dickson TEO ,  Karrthik PARATHITHASAN ,  Puay Han TAN

IPC: H01L21/02 ,  H01L21/683 ,  H01L21/324

Abstract: Methods and apparatus for reducing warpage of a substrate. In some embodiments, a method of reducing substrate warpage comprises heating the substrate with an epoxy layer to at least a glass transition temperature of the epoxy layer while allowing the substrate to expand; maintaining the at least the glass transition temperature of the substrate until the substrate is constrained; constraining the substrate with a total clamping force of approximately 5000N to approximately 7000N exerted towards the substrate from a top direction and a bottom direction; applying at least one electrostatic field to the substrate with a first electrostatic chuck positioned above the substrate and a second electrostatic chuck positioned below the substrate; and rapidly cooling the substrate using a first liquid convection heat sink positioned above the substrate and a second liquid convection heat sink positioned below the substrate.

公开(公告)号：US20240390950A1

公开(公告)日：2024-11-28

申请号：US18200539

申请日：2023-05-22

Applicant: Applied Materials, Inc.

Inventor： Ke ZHENG ,  Guan Huei SEE ,  Ying W. WANG ,  Ruiping WANG ,  Prayudi LIANTO

IPC: B08B1/00 ,  B08B1/02 ,  B08B3/02

Abstract: A brush box cleaning module is introduced as part of the pre-treatment process flow in an integrated hybrid bonding platform. It addresses the technical problem of achieving high cleanliness levels on die front-side and back-side surfaces, particularly by removing residues and particles induced by backgrinding tape and dicing tape. The brush box cleaning module efficiently removes stubborn residues and particles both chemically and mechanically, resulting in a clean and passivated surface without causing watermarks, scratches, corrosion, or surface roughness. This disclosed approach enhances the bonding yield and provides significant advantages over existing methods in die-stack hybrid bonding applications.

公开(公告)号：US20240110284A1

公开(公告)日：2024-04-04

申请号：US18372792

申请日：2023-09-26

Applicant: Applied Materials, Inc.

Inventor： Lulu XIONG ,  Kevin Hsiao ,  Chris LIU ,  Chieh-Wen LO ,  Sean M. SEUTTER ,  Deenesh PADHI ,  Prayudi LIANTO ,  Peng SUO ,  Guan Huei SEE ,  Zongbin WANG ,  Shengwei ZENG ,  Balamurugan RAMASAMY

IPC: C23C16/505 ,  C23C16/04 ,  C23C16/32 ,  C23C16/56 ,  H01J37/32

CPC classification number: C23C16/505 ,  C23C16/045 ,  C23C16/325 ,  C23C16/56 ,  H01J37/32165 ,  H01J37/3244 ,  H01J2237/3321

Abstract: A method of processing a substrate is disclosed which includes depositing a layer in a processing chamber on a field region, a sidewall region, and a fill region of a feature of the substrate, wherein a hardness of a portion of the layer deposited on the sidewall region is lower than a hardness of a portion of the layer deposited on the field region, and lower than a hardness of a portion of the layer deposited on the fill region.

公开(公告)号：US20220037216A1

公开(公告)日：2022-02-03

申请号：US16944285

申请日：2020-07-31

Applicant: APPLIED MATERIALS, INC.

Inventor： Prayudi LIANTO ,  Sik Hin CHI ,  Shih-Chao HUNG ,  Pin Gian GAN ,  Ricardo Fujii VINLUAN ,  Gaurav MEHTA ,  Ramesh CHIDAMBARAM ,  Guan Huei SEE ,  Arvind SUNDARRAJAN ,  Upendra V. UMMETHALA ,  Wei Hao KEW ,  Muhammad Adli Danish Bin ABDULLAH ,  Michael Charles KUTNEY ,  Mark McTaggart WYLIE ,  Amulya Ligorio ATHAYDE ,  Glen T. MORI

IPC: H01L21/66 ,  H01L21/768 ,  H01L21/304 ,  H01L21/306 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/683

Abstract: Methods and apparatus perform backside via reveal processes using a centralized control framework for multiple process tools. In some embodiments, a method for performing a backside via reveal process may include receiving process tool operational parameters from process tools involved in the backside via reveal process by a central controller, receiving sensor metrology data from at least one or more of the process tools involved in the backside via reveal process, and altering the backside reveal process based, at least in part, on the process tool operational parameters and the sensor metrology data by adjusting two or more of the process tools involved in the backside via reveal process. The profile parameters are configured to prevent backside via breakage during a chemical mechanical polishing (CMP) process.

公开(公告)号：US20180005881A1

公开(公告)日：2018-01-04

申请号：US15200836

申请日：2016-07-01

Applicant: APPLIED MATERIALS, INC.

Inventor： Prayudi LIANTO ,  Sam LEE ,  Charles SHARBONO ,  Marvin Louis BERNT ,  Guan Huei SEE ,  Arvind SUNDARRAJAN

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76879 ,  H01L21/76804 ,  H01L21/76873 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/5329

Abstract: A method of processing a semiconductor substrate includes: immersing a substrate in a first bath, wherein the substrate comprises a barrier layer, a conductive seed layer, and a patterned photoresist layer defining an opening; providing a first electric current between the conductive seed layer and a first anode disposed in electrical contact with the first bath to deposit a conductive material within the opening; stripping the patterned photoresist layer; immersing the substrate in a second bath; providing a second electric current that is a reverse of the first electric current between the conductive seed layer plus the conductive material and a second anode disposed in electrical contact with the second bath; etching the conductive seed layer from atop a field region of the barrier layer; and etching the barrier layer from atop a field region of the substrate.

公开(公告)号：US20240330671A1

公开(公告)日：2024-10-03

申请号：US18128496

申请日：2023-03-30

Applicant: Applied Materials, Inc.

Inventor： Rahul Reddy KOMATIREDDI ,  Rohith CHERIKKALLIL ,  Sneha Rupa KONGARA ,  Sachin DANGAYACH ,  Prayudi LIANTO ,  Peng SUO ,  Krishnaprasad Reddy MALLAVARAM ,  Satwik Swarup MISHRA ,  Si En CHAN ,  Remus Zhen Hui KOH ,  Khor Wui CHENG ,  Yin Wei LIM

IPC: G06N3/08

CPC classification number: G06N3/08

Abstract: A method and apparatus for training a learning model for the automatic detection and classification of defects on wafers includes receiving labeled images of wafer defects having multiple defect classifications, creating a first training set including the received labeled images of wafer defects, training the machine learning model to automatically detect and classify wafer defects in a first stage using the first training set, blending at least one set of at least two labeled images having different classifications to generate additional labeled image data, creating a second training set including the blended, additional labeled image data, and training the machine learning model to automatically detect and classify wafer defects in a second stage using the second training set. The trained machine learning model can then be applied to at least one unlabeled wafer image to determine at least one defect classification for the at least one unlabeled wafer image.

公开(公告)号：US20240069448A1

公开(公告)日：2024-02-29

申请号：US17900124

申请日：2022-08-31

Applicant: Applied Materials, Inc.

Inventor： Prayudi LIANTO ,  Liu JIANG ,  Marvin Louis BERNT ,  El Mehdi BAZIZI ,  Guan Huei SEE

IPC: G03F7/20 ,  G03F9/00

CPC classification number: G03F7/70633 ,  G03F9/7088

Abstract: A method for forming alignment marks leverages pad density and critical dimensions (CDs). In some embodiments, the method includes forming first and second alignment marks on a first substrate and a second substrate where the alignment marks have a width within 5% of the associated CD of copper pads on the respective substrates and forming a first and second dummy patterns around the first and second alignment marks. The first and second dummy patterns have dummy pattern densities within 5% of the respective copper pad density of the first and second substrates and CDs within 5% of the respective copper pad CDs. In some embodiments, alignment marks with physical dielectric material protrusions and recesses on opposite substrate surfaces may further enhance bonding.