公开(公告)号：US09299560B2

公开(公告)日：2016-03-29

申请号：US13736504

申请日：2013-01-08

Applicant: APPLIED MATERIALS, INC.

Inventor： Errol Antonio C. Sanchez ,  Yi-Chiau Huang ,  Xinyu Bao

IPC: H01L21/02 ,  H01L21/285 ,  H01L21/3065

CPC classification number: H01L21/0254 ,  H01L21/02636 ,  H01L21/28525 ,  H01L21/28556 ,  H01L21/3065

Abstract: Methods for depositing a group III-V layer on a substrate are disclosed herein. In some embodiments a method includes depositing a first layer comprising at least one of a first Group III element or a first Group V element on a silicon-containing surface oriented in a direction at a first temperature ranging from about 300 to about 400 degrees Celsius; and depositing a second layer comprising second Group III element and a second Group V element atop the first layer at a second temperature ranging from about 300 to about 600 degrees Celsius.

Abstract translation: 本文公开了在基板上沉积III-V族层的方法。 在一些实施方案中，一种方法包括在第一温度范围为约300至约400°的范围内沉积包含第一III族元素或第一V族元素中的至少一种的第一层在位于<111> 摄氏度 以及在约300至约600摄氏度的第二温度下沉积包含第二层第二组元素和第二组V元素的第二层。

公开(公告)号：US10204781B1

公开(公告)日：2019-02-12

申请号：US15896839

申请日：2018-02-14

Applicant: Applied Materials, Inc.

Inventor： Yung-Chen Lin ,  Qingjun Zhou ,  Xinyu Bao ,  Ying Zhang

IPC: H01L21/22 ,  H01L21/38 ,  H01L21/033 ,  H01L21/8234

Abstract: Embodiments described herein relate to substrate processing methods. The methods include forming a patterned hardmask material on a substrate, forming first mandrel structures on exposed regions of the substrate, and depositing a gap fill material on the substrate over the hardmask material and the first mandrel structures. The first mandrel structures are removed to expose second region of the substrate form second mandrel structures comprising the hardmask material and the gap fill material and fin structures are deposited on the substrate using the second mandrel structures as a mask.

公开(公告)号：US10043666B2

公开(公告)日：2018-08-07

申请号：US15055164

申请日：2016-02-26

Applicant: Applied Materials, Inc.

Inventor： Xinyu Bao ,  Errol Antonio C. Sanchez ,  Zhiyuan Ye ,  Keun-Yong Ban

IPC: H01L21/02 ,  H01L21/67 ,  C30B25/02

Abstract: Embodiments described herein generally relate to a substrate processing system, such as an etch processing system. In one embodiment, a method of processing a substrate is disclosed herein. The method includes removing a native oxide from a surface of the substrate, baking the substrate in a pre-treatment thermal chamber such that double atomic steps are formed on the surface of the substrate, and forming an epitaxial layer on the substrate after the substrate is baked.

公开(公告)号：US09852903B2

公开(公告)日：2017-12-26

申请号：US15416287

申请日：2017-01-26

Applicant: Applied Materials, Inc.

Inventor： Chun Yan ,  Xinyu Bao

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/3105

CPC classification number: H01L21/02546 ,  H01L21/02241 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/0234 ,  H01L21/02664 ,  H01L21/30621 ,  H01L21/3105 ,  H01L21/31122 ,  H01L29/66795

Abstract: A method for forming a group III-V semiconductor channel region in a transistor is provided herein. The method includes exposing a substrate including an oxide layer to a first plasma to treat the oxide layer, exposing the treated oxide layer to a second plasma to convert the oxide layer to an evaporable layer, evaporating the evaporable layer to expose a group III-V semiconductor material surface, and exposing the group III-V semiconductor material surface to an oxygen containing gas to oxidize the group III-V semiconductor material. The processes may be repeated until a recessed depth having a predetermined depth is formed. A group III-V semiconductor channel is then formed in the predetermined recessed depth. The control of the height of the group III-V semiconductor channel is improved.

公开(公告)号：US09799737B2

公开(公告)日：2017-10-24

申请号：US15185749

申请日：2016-06-17

Applicant: Applied Materials, Inc.

Inventor： Xinyu Bao ,  Errol Antonio C. Sanchez ,  David K. Carlson ,  Zhiyuan Ye

IPC: H01L29/205 ,  H01L29/267 ,  H01L21/02

CPC classification number: H01L29/205 ,  H01L21/02381 ,  H01L21/02455 ,  H01L21/02538 ,  H01L21/0262 ,  H01L21/02694 ,  H01L29/267 ,  Y10T117/1008

Abstract: A method for forming a conformal group III/V layer on a silicon substrate and the resulting substrate with the group III/V layers formed thereon. The method includes removing the native oxide from the substrate, positioning a substrate within a processing chamber, heating the substrate to a first temperature, cooling the substrate to a second temperature, flowing a group III precursor into the processing chamber, maintaining the second temperature while flowing a group III precursor and a group V precursor into the processing chamber until a conformal layer is formed, heating the processing chamber to an annealing temperature, while stopping the flow of the group III precursor, and cooling the processing chamber to the second temperature. Deposition of the III/V layer may be made selective through the use of halide gas etching which preferentially etches dielectric regions.

公开(公告)号：US09752224B2

公开(公告)日：2017-09-05

申请号：US15210030

申请日：2016-07-14

Applicant: Applied Materials, Inc.

Inventor： Zhiyuan Ye ,  Errol Antonio C. Sanchez ,  Keun-Yong Ban ,  Xinyu Bao

IPC: H01L21/02 ,  C23C8/02

CPC classification number: C23C8/02 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/0262

Abstract: Embodiments of the present disclosures provide methods and apparatus for manufacturing semiconductor devices such as transistors used for amplifying or switching electronic signals. Specifically, embodiments of the present disclosure generally relate to a semiconductor device having a film stack including an interlayer of semiconductor material and a buffer layer of semiconductor material underneath an active device layer. In various embodiments, the interlayer may include group III-V semiconductor materials formed between a first surface of a silicon-based substrate and the buffer layer. In certain embodiments the buffer layer may comprise group IV semiconductor materials. The interlayer may have a lattice constant designed to mitigate lattice mismatch between the group IV buffer layer and the silicon-based substrate. The buffer layer may provide improved integration of the active device layer to improve the performance of the resulting device.

公开(公告)号：US09653282B2

公开(公告)日：2017-05-16

申请号：US14445410

申请日：2014-07-29

Applicant: Applied Materials, Inc.

Inventor： Chun Yan ,  Xinyu Bao ,  Melitta Manyin Hon

IPC: H01L21/02

CPC classification number: H01L21/02046 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02658

Abstract: A method for cleaning a substrate, such as a silicon substrate, a silicon-germanium substrate, or other silicon-containing substrate is disclosed. The method includes exposing the substrate to a first plasma configured to attack a sub-oxide on the substrate. The method also includes exposing the substrate to a second plasma configured to attack the native oxide on the substrate. The method further includes exposing the substrate to a gas containing at least one of molecular chlorine or a chlorine compound. The gas may be configured to remove at least some of the remaining native oxide and sub-oxide. After the cleaning process, the substrate may be further processed. Further processing steps may include, for example, an epitaxial growth process. An epitaxial growth process performed on a substrate cleaned according to the methods disclosed herein will exhibit few defects.

公开(公告)号：US09373502B2

公开(公告)日：2016-06-21

申请号：US14287927

申请日：2014-05-27

Applicant: Applied Materials, Inc.

Inventor： Xinyu Bao ,  Errol Antonio C. Sanchez

IPC: H01L21/02 ,  H01L29/778 ,  H01L29/15

CPC classification number: H01L21/02463 ,  H01L21/02381 ,  H01L21/02502 ,  H01L21/02546 ,  H01L21/0262 ,  H01L29/15 ,  H01L29/7783

Abstract: Embodiments described herein relate to a structure for III-V devices on silicon. A Group IV substrate is provided and a III-V structure may be formed thereon. The III-V structure generally comprises one or more buffer layers and a channel layer disposed on the one or more buffer layers. The one or more buffer layers may be selected to provide optimal microelectronic device properties, such as minimal defects, reduced charge accumulation, and reduced current leakage.

Abstract translation: 本文描述的实施例涉及硅上III-V器件的结构。 提供IV族基板，并且可以在其上形成III-V结构。 III-V结构通常包括一个或多个缓冲层和设置在一个或多个缓冲层上的通道层。 可以选择一个或多个缓冲层以提供最佳的微电子器件性质，例如最小的缺陷，减少的电荷累积和减少的电流泄漏。

公开(公告)号：US10256322B2

公开(公告)日：2019-04-09

申请号：US15926921

申请日：2018-03-20

Applicant: Applied Materials, Inc.

Inventor： Xinyu Bao ,  Zhiyuan Ye ,  Hua Chung

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/78 ,  H01L29/167 ,  H01L29/08 ,  H01L29/06

Abstract: A device comprising Si:As source and drain extensions and Si:As or Si:P source and drain features formed using selective epitaxial growth and a method of forming the same is provided. The epitaxial layers used for the source and drain extensions and the source and drain features herein are deposited by simultaneous film formation and film etching, wherein the deposited material on the monocrystalline layer is etched at a slower rate than deposition material deposited on non-monocrystalline location of a substrate. As a result, an epitaxial layer is deposited on the monocrystalline surfaces, and a layer is not deposited on non-monocrystalline surfaces of the same base material, such as silicon.

公开(公告)号：US10243063B2

公开(公告)日：2019-03-26

申请号：US15617613

申请日：2017-06-08

Applicant: Applied Materials, Inc.

Inventor： Chun Yan ,  Xinyu Bao

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/04

Abstract: Embodiments described herein generally provide a method and apparatus to form semiconductor devices. Specifically, embodiments describe an apparatus and methods of forming channels in sub-5 nm node FinFETS. The method provides for various processing steps to deposit a dielectric layer over a substrate. The method continues by etching a trench in the dielectric layer, depositing a silicon layer within the trench, depositing a buffer layer on top of the silicon layer in the trench, removing a portion of the buffer layer to form a planar surface, etching the buffer layer into a v-shape, and depositing a channel layer on top of the v-shaped buffer layer. The v-shaped buffer layer advantageously negates facet formation and provides for an InGaAs fin-channel with uniform distribution of indium and gallium throughout the channel.