公开(公告)号：US11649559B2

公开(公告)日：2023-05-16

申请号：US16266646

申请日：2019-02-04

Applicant: Applied Materials, Inc.

Inventor： Xinyu Bao ,  Chun Yan ,  Hua Chung ,  Schubert S. Chu

IPC: C30B25/16 ,  C30B25/08 ,  C30B25/00 ,  C30B33/00 ,  C23C16/44 ,  C23C16/30 ,  C23C16/48 ,  C23C16/56 ,  C30B25/10 ,  C30B25/12 ,  C30B25/14 ,  C30B29/40 ,  H01L21/67 ,  C30B35/00 ,  H01L21/225 ,  H01L21/30 ,  C30B29/06

CPC classification number: C30B25/08 ,  C23C16/301 ,  C23C16/4405 ,  C23C16/481 ,  C23C16/56 ,  C30B25/00 ,  C30B25/105 ,  C30B25/12 ,  C30B25/14 ,  C30B25/165 ,  C30B29/40 ,  C30B33/00 ,  C30B35/00 ,  H01L21/67167 ,  H01L21/67196 ,  H01L21/67207 ,  H01L21/67253 ,  C30B29/06 ,  H01L21/2252 ,  H01L21/30 ,  H01L21/67201

Abstract: Implementations of the present disclosure generally relate to the fabrication of integrated circuits. More specifically, implementations disclosed herein relate to apparatus, systems, and methods for reducing substrate outgassing. A substrate is processed in an epitaxial deposition chamber for depositing an arsenic-containing material on a substrate and then transferred to a degassing chamber for reducing arsenic outgassing on the substrate. The degassing chamber includes a gas panel for supplying hydrogen, nitrogen, and oxygen and hydrogen chloride or chlorine gas to the chamber, a substrate support, a pump, and at least one heating mechanism. Residual or fugitive arsenic is removed from the substrate such that the substrate may be removed from the degassing chamber without dispersing arsenic into the ambient environment.

公开(公告)号：US10770568B2

公开(公告)日：2020-09-08

申请号：US16277634

申请日：2019-02-15

Applicant: Applied Materials, Inc.

Inventor： Xinyu Bao ,  Ying Zhang ,  Qingjun Zhou ,  YungChen Lin

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/762

Abstract: Methods for forming semiconductor devices, such as FinFETs, are provided. In an embodiment, a fin structure processing method includes removing a portion of a first fin of a plurality of fins formed on a substrate to expose a surface of a remaining portion of the first fin, wherein the fins are adjacent to dielectric material structures formed on the substrate; performing a deposition operation to form features on the surface of the remaining portion of the first fin by depositing a Group III-V semiconductor material in a substrate processing environment; and performing an etching operation to etch the features with an etching gas to form a plurality of openings between adjacent dielectric material structures, wherein the etching operation is performed in the same chamber as the deposition operation.

公开(公告)号：US10438796B2

公开(公告)日：2019-10-08

申请号：US15496420

申请日：2017-04-25

Applicant: Applied Materials, Inc.

Inventor： Chun Yan ,  Xinyu Bao

IPC: H01L21/02 ,  B08B7/00 ,  H01L21/67 ,  B08B7/04 ,  B08B5/00

Abstract: Native oxides and residue are removed from surfaces of a substrate by performing a multiple-stage native oxide cleaning process. In one example, the method for removing native oxides from a substrate includes supplying a first gas mixture including an inert gas onto a surface of a material layer disposed on a substrate into a first processing chamber, wherein the material layer is a III-V group containing layer for a first period of time, supplying a second gas mixture including an inert gas and a hydrogen containing gas onto the surface of the material layer for a second period of time, and supplying a third gas mixture including a hydrogen containing gas to the surface of the material layer while maintaining the substrate at a temperature less than 550 degrees Celsius.

公开(公告)号：US10332739B2

公开(公告)日：2019-06-25

申请号：US15417466

申请日：2017-01-27

Applicant: Applied Materials, Inc.

Inventor： Chun Yan ,  Xinyu Bao ,  Hua Chung ,  Schubert S. Chu

IPC: H01L21/02 ,  B08B7/00 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/67 ,  C23C16/44 ,  C23C16/56

Abstract: Implementations disclosed herein relate to methods for controlling substrate outgassing of hazardous gasses after an epitaxial process. In one implementation, the method includes providing a substrate comprising an epitaxial layer into a transfer chamber, wherein the transfer chamber has an ultraviolet (UV) lamp module disposed adjacent to a top ceiling of the transfer chamber, flowing an oxygen-containing gas into the transfer chamber through a gas line of the transfer chamber, flowing a non-reactive gas into the transfer chamber through the gas line of the transfer chamber, activating the UV lamp module to oxidize residues or species on a surface of the substrate to form an outgassing barrier layer on the surface of the substrate, ceasing the flow of the oxygen-containing gas and the nitrogen-containing gas into the transfer chamber, pumping the transfer chamber, and deactivating the UV lamp module.

公开(公告)号：US10269647B2

公开(公告)日：2019-04-23

申请号：US15811188

申请日：2017-11-13

Applicant: Applied Materials, Inc.

Inventor： Ying Zhang ,  Schubert S. Chu ,  Xinyu Bao ,  Regina Germanie Freed ,  Hua Chung

IPC: H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238

Abstract: Methods for forming semiconductor devices, such as FinFETs, are provided. In one embodiment, a method for forming a FinFET device includes removing a portion of each fin of a plurality of fins, and a remaining portion of each fin is recessed from a dielectric surface. The method further includes forming a feature on the remaining portion of each fin, filling gaps formed between adjacent features with a dielectric material, removing the features, and forming a fill material on the remaining portion of each fin. Because the shape of the features is controlled, the shape of the fill material can be controlled.

公开(公告)号：US10224421B2

公开(公告)日：2019-03-05

申请号：US15933072

申请日：2018-03-22

Applicant: Applied Materials, Inc.

Inventor： Zhiyuan Ye ,  Xinyu Bao ,  Chun Yan ,  Hua Chung ,  Schubert S. Chu ,  Satheesh Kuppurao

IPC: H01L29/26 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/8252 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/027 ,  H01L21/67

Abstract: Methods of sub-10 nm fin formation are disclosed. One method includes patterning a first dielectric layer on a substrate to form one or more projections and a first plurality of spaces, and depositing a first plurality of columns in the first plurality of spaces. The first plurality of columns are separated by a second plurality of spaces. The method also includes depositing a second dielectric layer in the second plurality of spaces to form a plurality of dummy fins, removing the first plurality of columns to form a third plurality of spaces, depositing a second plurality of columns in the third plurality of spaces, removing the one or more projections and the plurality of dummy fins to form a fourth plurality of spaces, and depositing a plurality of fins in the fourth plurality of spaces. The plurality of fins have a width between 5-10 nm.

公开(公告)号：US10236190B2

公开(公告)日：2019-03-19

申请号：US15588641

申请日：2017-05-06

Applicant: Applied Materials, Inc.

Inventor： Chun Yan ,  Xinyu Bao

IPC: H01L21/302 ,  H01L21/67 ,  H01L21/3065 ,  H01L21/306

Abstract: Embodiments disclosed herein generally relate to methods for controlling substrate outgassing such that hazardous gasses are eliminated from a surface of a substrate after a III-V epitaxial growth process or an etch clean process, and prior to additional processing. An oxygen containing gas is flowed to a substrate in a load lock chamber, and subsequently a non-reactive gas is flowed to the substrate in the load lock chamber. As such, hazardous gases and outgassing residuals are decreased and/or removed from the substrate such that further processing may be performed.

公开(公告)号：US10090147B2

公开(公告)日：2018-10-02

申请号：US15890117

申请日：2018-02-06

Applicant: Applied Materials, Inc.

Inventor： Chun Yan ,  Xinyu Bao ,  Melitta Manyin Hon ,  Hua Chung ,  Schubert S. Chu

IPC: H01L21/02 ,  H01L29/66

Abstract: Implementations described herein generally provide a method of processing a substrate. Specifically, the methods described are used for cleaning and etching source/drain regions on a silicon substrate in preparation for precise Group IV source/drain growth in semiconductor devices. Benefits of this disclosure include precise fin size control in devices, such as 10 nm FinFET devices, and increased overall device yield. The method of integrated clean and recess includes establishing a low pressure processing environment in the processing volume, and maintaining the low pressure processing environment while flowing a first gas over a substrate in a processing volume, depositing a salt on the substrate, heating the processing volume to greater than 90° C., purging the processing volume with a second inert gas, and recessing a source/drain region disposed on the substrate.

公开(公告)号：US10043667B2

公开(公告)日：2018-08-07

申请号：US15418190

申请日：2017-01-27

Applicant: Applied Materials, Inc.

Inventor： Chun Yan ,  Xinyu Bao ,  Hua Chung ,  Schubert S. Chu

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/08 ,  C23C14/58 ,  H01L21/20 ,  C23C14/02 ,  H01L21/768 ,  H01L21/203

Abstract: Implementations disclosed herein relate to methods for controlling substrate outgassing. In one implementation, the method includes removing oxides from an exposed surface of a substrate in an inductively coupled plasma chamber, forming an epitaxial layer on the exposed surface of the substrate in an epitaxial deposition chamber, and performing an outgassing control of the substrate by subjecting the substrate to a first plasma formed from a first etch precursor in the inductively coupled plasma chamber at a first chamber pressure, wherein the first etch precursor comprises a hydrogen-containing precursor, a chlorine-containing precursor, and an inert gas, and subjecting the substrate to a second plasma formed from a second etch precursor in the inductively coupled plasma chamber at a second chamber pressure that is higher than the first chamber pressure, wherein the second etch precursor comprises a hydrogen-containing precursor and an inert gas.

公开(公告)号：US09530888B2

公开(公告)日：2016-12-27

申请号：US15073245

申请日：2016-03-17

Applicant: Applied Materials, Inc.

Inventor： Keun-Yong Ban ,  Zhiyuan Ye ,  Errol Antonio C. Sanchez ,  Xinyu Bao ,  David K. Carlson

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/04 ,  H01L29/205 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/7849 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02439 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66522

Abstract: Embodiments of the present disclosure generally relate to a semiconductor device including layers of group III-V semiconductor materials. In one embodiment, the semiconductor device includes a phosphorous containing layer deposited on a silicon substrate, wherein a lattice mismatch between the phosphorous containing layer and the silicon substrate is less than 5%, a group III-V compound nucleation layer deposited on the phosphorous containing layer at a first temperature, the group III-V compound nucleation layer having a first thickness, a group III-V compound transition layer deposited on the group III-V compound nucleation layer at a second temperature higher than the first temperature, the group III-V compound transition layer having a second thickness larger than the first thickness, and the group III-V compound nucleation layer is different from the group III-V compound transition layer, and an active layer deposited on the group III-V compound transition layer.

Abstract translation: 本公开的实施例一般涉及包括III-V族III族半导体材料层的半导体器件。 在一个实施例中，半导体器件包括沉积在硅衬底上的含磷层，其中含磷层和硅衬底之间的晶格失配小于5％，III-V族化合物成核层沉积在含磷 III族化合物成核层，第III-V族化合物成核层，第III-V族化合物成核层，第III-V族化合物成核层，第III-V族化合物成核层， -V化合物过渡层，其具有大于第一厚度的第二厚度，III-V族化合物成核层与III-V族化合物过渡层不同，并且沉积在III-V族化合物过渡层上的活性层 。