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公开(公告)号:US20230005765A1
公开(公告)日:2023-01-05
申请号:US17366761
申请日:2021-07-02
Applicant: Applied Materials, Inc.
Inventor: Son T. Nguyen , Kenneth D. Schatz , Anh N. Nguyen , Soonwook Jung , Ryan Pakulski , Anchuan Wang , Zihui Li
Abstract: Exemplary semiconductor processing systems may include a processing chamber. The systems may include a remote plasma unit coupled with the processing chamber. The systems may include an adapter coupled between the remote plasma unit and the processing chamber. The adapter may be characterized by a first end and a second end opposite the first end. The remote plasma unit may be coupled with the adapter at the first end. The adapter may define a first central channel extending more than 50% of a length of the adapter from the first end of the adapter. The adapter may define a second central channel extending less than 50% of the length of the adapter from the second end of the adapter. The adapter may define a transition between the first central channel and the second central channel.
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公开(公告)号:US20160064233A1
公开(公告)日:2016-03-03
申请号:US14936448
申请日:2015-11-09
Applicant: Applied Materials, Inc.
Inventor: Anchuan Wang , Xinglong Chen , Zihui Li , Hiroshi Hamana , Zhijun Chen , Ching-Mei Hsu , Jiayin Huang , Nitin K. Ingle , Dmitry Lubomirsky , Shankar Venkataraman , Randhir Thakur
IPC: H01L21/3065
CPC classification number: H01L21/324 , C23C16/4405 , H01J37/32357 , H01J37/32862 , H01L21/02041 , H01L21/02057 , H01L21/0206 , H01L21/263 , H01L21/2686 , H01L21/30604 , H01L21/3065 , H01L21/3105 , H01L21/31111 , H01L21/31116 , H01L21/31144 , H01L21/32136 , H01L21/32137 , H01L21/67069 , H01L21/67075 , H01L21/6708 , H01L21/67109 , H01L21/67115 , H01L21/67184 , H01L21/6719 , H01L21/67196 , H01L21/67201 , H01L21/67207 , H01L21/67248 , H01L21/67253 , H01L21/67288 , H01L21/67703 , H01L21/67739 , H01L21/67742 , H01L21/6831
Abstract: Systems, chambers, and processes are provided for controlling process defects caused by moisture contamination. The systems may provide configurations for chambers to perform multiple operations in a vacuum or controlled environment. The chambers may include configurations to provide additional processing capabilities in combination chamber designs. The methods may provide for the limiting, prevention, and correction of aging defects that may be caused as a result of etching processes performed by system tools.
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公开(公告)号:US20150371866A1
公开(公告)日:2015-12-24
申请号:US14309625
申请日:2014-06-19
Applicant: Applied Materials, Inc.
Inventor: Zhijun Chen , Zihui Li , Nitin K. Ingle , Anchuan Wang , Shankar Venkataraman
IPC: H01L21/311 , H01L21/02
CPC classification number: H01L21/31116 , H01J37/32357 , H01J2237/334 , H01L21/02164 , H01L21/0337 , H01L21/31138 , H01L21/31144 , H01L21/32139 , H01L21/70
Abstract: A method of etching doped silicon oxide on patterned heterogeneous structures is described and includes a gas phase etch using partial remote plasma excitation. The remote plasma excites a fluorine-containing precursor and the plasma effluents created are flowed into a substrate processing region. A hydrogen-containing precursor, e.g. water, is concurrently flowed into the substrate processing region without plasma excitation. The plasma effluents are combined with the unexcited hydrogen-containing precursor in the substrate processing region where the combination reacts with the doped silicon oxide. The plasmas effluents react with the patterned heterogeneous structures to selectively remove doped silicon oxide.
Abstract translation: 描述了在图案化的异质结构上蚀刻掺杂的氧化硅的方法,并且包括使用部分远程等离子体激发的气相蚀刻。 远程等离子体激发含氟前体,产生的等离子体流出物流入基板处理区域。 含氢前体,例如 水同时流入基板处理区域而没有等离子体激发。 在衬底处理区域中,等离子体流出物与未掺杂的含氢前体结合,其中组合与掺杂的氧化硅反应。 等离子体流出物与图案化的异质结构反应以选择性地去除掺杂的氧化硅。
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公开(公告)号:US09209012B2
公开(公告)日:2015-12-08
申请号:US14479671
申请日:2014-09-08
Applicant: Applied Materials, Inc.
Inventor: Zhijun Chen , Zihui Li , Anchuan Wang , Nitin K. Ingle , Shankar Venkataraman
IPC: H01L21/302 , H01L21/461 , H01L21/02 , H01L21/311 , H01L21/3065 , H01J37/32
CPC classification number: H01L21/02205 , H01J37/32357 , H01J2237/334 , H01L21/3065 , H01L21/31116
Abstract: A method of etching silicon nitride on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor and a nitrogen-and-oxygen-containing precursor. Plasma effluents from two remote plasmas are flowed into a substrate processing region where the plasma effluents react with the silicon nitride. The plasmas effluents react with the patterned heterogeneous structures to selectively remove silicon nitride while very slowly removing silicon, such as polysilicon. The silicon nitride selectivity results partly from the introduction of fluorine-containing precursor and nitrogen-and-oxygen-containing precursor using distinct (but possibly overlapping) plasma pathways which may be in series or in parallel.
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公开(公告)号:US09184055B2
公开(公告)日:2015-11-10
申请号:US14246952
申请日:2014-04-07
Applicant: APPLIED MATERIALS, INC.
Inventor: Anchuan Wang , Xinglong Chen , Zihui Li , Hiroshi Hamana , Zhijun Chen , Ching-Mei Hsu , Jiayin Huang , Nitin K. Ingle , Dmitry Lubomirsky , Shankar Venkataraman , Randhir Thakur
IPC: H01L21/263 , H01L21/02 , H01L21/67 , C23C16/44 , H01L21/677 , H01L21/306 , H01L21/3065 , H01L21/683 , H01L21/3213 , H01L21/311 , H01J37/32
CPC classification number: H01L21/324 , C23C16/4405 , H01J37/32357 , H01J37/32862 , H01L21/02041 , H01L21/02057 , H01L21/0206 , H01L21/263 , H01L21/2686 , H01L21/30604 , H01L21/3065 , H01L21/3105 , H01L21/31111 , H01L21/31116 , H01L21/31144 , H01L21/32136 , H01L21/32137 , H01L21/67069 , H01L21/67075 , H01L21/6708 , H01L21/67109 , H01L21/67115 , H01L21/67184 , H01L21/6719 , H01L21/67196 , H01L21/67201 , H01L21/67207 , H01L21/67248 , H01L21/67253 , H01L21/67288 , H01L21/67703 , H01L21/67739 , H01L21/67742 , H01L21/6831
Abstract: Systems, chambers, and processes are provided for controlling process defects caused by moisture contamination. The systems may provide configurations for chambers to perform multiple operations in a vacuum or controlled environment. The chambers may include configurations to provide additional processing capabilities in combination chamber designs. The methods may provide for the limiting, prevention, and correction of aging defects that may be caused as a result of etching processes performed by system tools.
Abstract translation: 提供系统,室和过程以控制由水分污染引起的过程缺陷。 这些系统可以提供腔室的配置,以在真空或受控环境中执行多个操作。 腔室可以包括在组合腔室设计中提供附加处理能力的构造。 这些方法可以提供由系统工具执行的蚀刻工艺可能引起的老化缺陷的限制,预防和校正。
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公开(公告)号:US20150235865A1
公开(公告)日:2015-08-20
申请号:US14703299
申请日:2015-05-04
Applicant: Applied Materials, Inc.
Inventor: Anchuan Wang , Xinglong Chen , Zihui Li , Hiroshi Hamana , Zhijun Chen , Ching-Mei Hsu , Jiayin Huang , Nitin K. Ingle , Dmitry Lubomirsky , Shankar Venkataraman , Randhir Thakur
IPC: H01L21/324 , H01L21/306 , H01L21/311 , H01L21/3065
CPC classification number: H01L21/324 , C23C16/4405 , H01J37/32357 , H01J37/32862 , H01L21/02041 , H01L21/02057 , H01L21/0206 , H01L21/263 , H01L21/2686 , H01L21/30604 , H01L21/3065 , H01L21/3105 , H01L21/31111 , H01L21/31116 , H01L21/31144 , H01L21/32136 , H01L21/32137 , H01L21/67069 , H01L21/67075 , H01L21/6708 , H01L21/67109 , H01L21/67115 , H01L21/67184 , H01L21/6719 , H01L21/67196 , H01L21/67201 , H01L21/67207 , H01L21/67248 , H01L21/67253 , H01L21/67288 , H01L21/67703 , H01L21/67739 , H01L21/67742 , H01L21/6831
Abstract: Systems, chambers, and processes are provided for controlling process defects caused by moisture contamination. The systems may provide configurations for chambers to perform multiple operations in a vacuum or controlled environment. The chambers may include configurations to provide additional processing capabilities in combination chamber designs. The methods may provide for the limiting, prevention, and correction of aging defects that may be caused as a result of etching processes performed by system tools.
Abstract translation: 提供系统,室和过程以控制由水分污染引起的过程缺陷。 这些系统可以提供腔室的配置,以在真空或受控环境中执行多个操作。 腔室可以包括在组合腔室设计中提供附加处理能力的构造。 这些方法可以提供由系统工具执行的蚀刻工艺可能引起的老化缺陷的限制,预防和校正。
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公开(公告)号:US08956980B1
公开(公告)日:2015-02-17
申请号:US14089182
申请日:2013-11-25
Applicant: Applied Materials, Inc.
Inventor: Zhijun Chen , Zihui Li , Anchuan Wang , Nitin K. Ingle , Shankar Venkataraman
IPC: H01L21/302 , H01L21/461 , H01L21/311
CPC classification number: H01L21/02205 , H01J37/32357 , H01J2237/334 , H01L21/3065 , H01L21/31116
Abstract: A method of etching silicon nitride on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor and a nitrogen-and-oxygen-containing precursor. Plasma effluents from two remote plasmas are flowed into a substrate processing region where the plasma effluents react with the silicon nitride. The plasmas effluents react with the patterned heterogeneous structures to selectively remove silicon nitride while very slowly removing silicon, such as polysilicon. The silicon nitride selectivity results partly from the introduction of fluorine-containing precursor and nitrogen-and-oxygen-containing precursor using distinct (but possibly overlapping) plasma pathways which may be in series or in parallel.
Abstract translation: 描述了在图案化的异质结构上蚀刻氮化硅的方法,并且包括由含氟前体和含氮和氧的前体形成的远程等离子体蚀刻。 来自两个远程等离子体的等离子体流出物流入基板处理区域,其中等离子体流出物与氮化硅反应。 等离子体流出物与图案化的异质结构反应以选择性地去除氮化硅,同时非常缓慢地除去硅,例如多晶硅。 氮化硅选择性部分取决于使用可能是串联或并联的不同(但可能重叠的)等离子体途径引入含氟前体和含氮和氧的前体。
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公开(公告)号:US20230102558A1
公开(公告)日:2023-03-30
申请号:US17487596
申请日:2021-09-28
Applicant: Applied Materials, Inc.
Inventor: Arvind Kumar , Mahendra Pakala , Ellie Y. Yieh , John Tolle , Thomas Kirschenheiter , Anchuan Wang , Zihui Li
IPC: H01L27/108 , H01L29/06 , H01L29/786 , H01L21/02 , H01L21/306 , H01L29/66
Abstract: Methods of reducing wafer bowing in 3D DRAM devices are described using a 3-color process. A plurality of film stacks are formed on a substrate surface, each of the film stacks comprises two doped SiGe layers having different dopant amounts and/or Si:Ge ratios and a doped silicon layer. 3D DRAM devices are also described.
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公开(公告)号:US20190326123A1
公开(公告)日:2019-10-24
申请号:US16435910
申请日:2019-06-10
Applicant: Applied Materials, Inc.
Inventor: Zihui Li , Rui Cheng , Anchuan Wang , Nitin K. Ingle , Abhijit Basu Mallick
IPC: H01L21/3065
Abstract: Exemplary methods for selectively removing silicon (e.g. polysilicon) from a patterned substrate may include flowing a fluorine-containing precursor into a substrate processing chamber to form plasma effluents. The plasma effluents may remove silicon (e.g. polysilicon, amorphous silicon or single crystal silicon) at significantly higher etch rates compared to exposed silicon oxide, silicon nitride or other dielectrics on the substrate. The methods rely on the temperature of the substrate in combination with some conductivity of the surface to catalyze the etch reaction rather than relying on a gas phase source of energy such as a plasma.
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公开(公告)号:US10319600B1
公开(公告)日:2019-06-11
申请号:US15918860
申请日:2018-03-12
Applicant: Applied Materials, Inc.
Inventor: Zihui Li , Rui Cheng , Anchuan Wang , Nitin K. Ingle , Abhijit Basu Mallick
IPC: H01L21/3065 , H01L21/311
Abstract: Exemplary methods for selectively removing silicon (e.g. polysilicon) from a patterned substrate may include flowing a fluorine-containing precursor into a substrate processing chamber to form plasma effluents. The plasma effluents may remove silicon (e.g. polysilicon, amorphous silicon or single crystal silicon) at significantly higher etch rates compared to exposed silicon oxide, silicon nitride or other dielectrics on the substrate. The methods rely on the temperature of the substrate in combination with some conductivity of the surface to catalyze the etch reaction rather than relying on a gas phase source of energy such as a plasma.
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