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公开(公告)号：US20230003795A1
公开(公告)日：2023-01-05
申请号：US17363809
申请日：2021-06-30
Applicant: Arm Limited
Inventor： Fernando Garcia Redondo , James Edward Myers , Parameshwarappa Anand Kumar Savanth , Pranay Prabhat , Gary Dale Carpenter
IPC: G01R31/317 , G06F9/4401
Abstract: Subject matter disclosed herein may relate to wireless energy harvesting devices and may relate more particularly to system-on-a-chip testing for wireless energy harvesting devices.
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公开(公告)号：US20210143801A1
公开(公告)日：2021-05-13
申请号：US17157483
申请日：2021-01-25
Applicant: Arm Limited
Inventor： Philex Ming-Yan Fan , Parameshwarappa Anand Kumar Savanth , Benoit Labbe , Bal S. Sandhu , Pranay Prabhat , James Edward Myers
IPC: H03K3/0231 , H02M3/07
Abstract: Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has a step-down converter coupled to an oscillator between a first voltage supply and a second voltage supply. The second stage is coupled to the first stage, and the second stage has a current bias generator coupled to a diode-connected transistor between the first voltage supply and the second voltage supply. The second stage provides an intermediate voltage to the first stage.
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公开(公告)号：US20170294222A1
公开(公告)日：2017-10-12
申请号：US15093457
申请日：2016-04-07
Applicant: ARM Limited
Inventor： Parameshwarappa Anand Kumar Savanth , James Edward Myers , Pranay Prabhat , David Walter Flynn , Shidhartha Das , David Michael Bull
IPC: G11C11/419 , G11C5/06
CPC classification number: G11C11/419 , G11C5/063 , G11C11/4125
Abstract: A storage bitcell comprising a first inverter cross-coupled with a second inverter, both the first and second inverter being in a path between a first potential and a second potential; wherein a first isolator is connected in the path between the first inverter and the first potential. The storage bitcell has particular application as Static Random-Access Memory (SRAM) circuitry.
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公开(公告)号：US09496785B2
公开(公告)日：2016-11-15
申请号：US14922783
申请日：2015-10-26
Applicant: ARM Limited
Inventor： Parameshwarappa Anand Kumar Savanth , James Edward Myers , David Walter Flynn , Bal S. Sandhu
CPC classification number: H02M3/157 , G01R19/0084 , H02M3/07 , Y02B70/16
Abstract: An integrated circuit has voltage generating circuitry for generating an on-chip voltage from a supply voltage in response to clock pulses. Clock control circuitry controls transmission of the clock pulses to the voltage generating circuitry. The clock control circuitry receives a reference voltage and a digital offset value comprising a binary numeric value identifying an offset. The clock control circuitry suppresses transmission of the clock pulses if the on-chip voltage is greater than the sum of the reference voltage and the offset identified by the digital offset value, to reduce power consumption. The offset can be tuned digitally to vary the average level of the on-chip voltage. A similar digital tuning mechanism may be used in a clocked comparator to compare a first voltage with a digitally tunable threshold voltage.
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公开(公告)号：US11714564B2
公开(公告)日：2023-08-01
申请号：US16735606
申请日：2020-01-06
Applicant: Arm Limited
Inventor： James Edward Myers , Pranay Prabhat , Matthew James Walker , Parameshwarappa Anand Kumar Savanth , Fernando Garcia Redondo
IPC: G06F1/00 , G06F3/06 , G06F1/3234 , G06F1/324 , G06F1/3296 , G06F1/3209 , G06F1/3221
CPC classification number: G06F3/0634 , G06F1/324 , G06F1/3234 , G06F1/3296 , G06F3/0625 , G06F1/3209 , G06F1/3221 , G06F3/0689
Abstract: According to one implementation of the present disclosure, a method for power management is disclosed. The method includes: computing, by a central processing unit, software instructions of a software workload in an active-mode operation corresponding to a first operating point on a performance curve of a performance mode; transitioning from instances of the active-mode operation to instances of standby-mode operation of the CPU, and recording, by a time tracking element, each of a plurality of standby entry data points; transitioning from the instances of the standby-mode operation to the instances of the active-mode operation of the CPU, and recording, by the time tracking element, each of a plurality of standby exit data points; and determining a second operating point on the performance curve of the performance mode based on the recorded standby entry data points and the recorded standby exit data points.
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Patent Agency Ranking
公开(公告)号：US11200384B2
公开(公告)日：2021-12-14
申请号：US16817496
申请日：2020-03-12
Applicant: Arm Limited
Abstract: Disclosed are methods, systems and devices for allocating a power signal. In one particular implementation, a reader device may exchange messages with one more transponder devices to determine an allocation of a power signal. For example, one or more transponder devices may provide one or more messages in a downlink signal indicative of a requested signal up time.
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公开(公告)号：US20210026389A1
公开(公告)日：2021-01-28
申请号：US16520112
申请日：2019-07-23
Applicant: Arm Limited
Abstract: Various implementations described herein are directed to multi-stage system. The system may include a first stage having a current bias generator that generates a biasing current. The system may include a second stage that is coupled to the first stage, and the second stage may include a load that utilizes the biasing current generated by the current bias generator.
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公开(公告)号：US10664031B2
公开(公告)日：2020-05-26
申请号：US15361405
申请日：2016-11-26
Applicant: ARM Limited
Inventor： Parameshwarappa Anand Kumar Savanth , Bal S. Sandhu , James Edward Myers , Alexander Stewart Weddell , David Walter Flynn
IPC: G06F1/00 , G06F1/28 , G01R19/165
Abstract: Broadly speaking, embodiments of the present techniques provide a voltage monitoring circuit for low power minimum-energy sensor nodes. The circuit comprises sensing circuitry to sense a monitored signal having a plurality of operating signal states; a first comparator having a first input for receiving an upper threshold signal; and a second comparator having a first input for receiving a lower threshold signal, the upper and lower threshold signals defining a range which includes at least one signal state of the plurality of operating states of the monitored signal, wherein the first and second comparators have a bias input for receiving a bias configuration setting, the bias configuration setting being selectable according to an operating signal state of the monitored signal.
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公开(公告)号：US10651683B2
公开(公告)日：2020-05-12
申请号：US15313599
申请日：2015-05-11
Applicant: ARM Limited
Abstract: An electronic device 50 has at least one harvesting unit 52 for harvesting power from ambient energy. At least one circuit 54, including processing circuitry 56, is supplied with power from the harvesting unit 52. Control circuitry 60 is provided to adjust at least one property of the processing circuitry 56 or the at least one harvesting unit 52 to reduce impedance mismatch between an output impedance of the harvesting unit 52 and an input impedance of the at least one circuit 54.
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公开(公告)号：US20200089266A1
公开(公告)日：2020-03-19
申请号：US16130938
申请日：2018-09-13
Applicant: Arm Limited
IPC: G05F3/24 , G05F1/46 , G11C5/14 , G11C11/4074
Abstract: Briefly, embodiments of claimed subject matter relate to comparison of a signal amplitude, such as a signal originating from a battery, for example, with a reference signal. A reference signal may be generated via body-biasing of one or more transistors, for example, which permit operation of the one or more transistors in a sub-threshold state, in which current through the one or more transistors comprises an exponential relationship to an applied voltage. Thus, at least in particular embodiments, detection of low battery voltage or battery overvoltage may be performed utilizing only a very small amount of electrical power
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