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公开(公告)号：US09946319B2
公开(公告)日：2018-04-17
申请号：US14059384
申请日：2013-10-21
Applicant: Advanced Micro Devices, Inc.
Inventor： Indrani Paul , Manish Arora , Srilatha Manne , William L. Bircher
CPC classification number: G06F1/3206 , G06F1/206
Abstract: The described embodiments include a computing device with a first entity and a second entity. In the computing device, a management controller dynamically sets a power-state limit for the first entity based on a performance coupling and a thermal coupling between the first entity and the second entity.
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公开(公告)号：US20180088606A1
公开(公告)日：2018-03-29
申请号：US15274697
申请日：2016-09-23
Applicant: Advanced Micro Devices, Inc.
Inventor： Wei Huang , Yazhou Zu , Indrani Paul
CPC classification number: G06F1/28 , G06F1/3206 , G06F1/3296 , Y02D10/172
Abstract: A method and apparatus for managing processing power determine a supply voltage to supply to a processing unit, such as a central processing unit (CPU) or graphics processing unit (GPU), based on temperature inversion based voltage, frequency, temperature (VFT) data. The temperature inversion based VFT data includes supply voltages and corresponding operating temperatures that cause the processing unit's transistors to operate in a temperature inversion region. In one example, the temperature inversion based VFT data includes lower supply voltages and corresponding higher temperatures in a temperature inversion region of a processing unit. The temperature inversion based VFT data is based on an operating frequency of the processing unit. The apparatus and method adjust a supply voltage to the processing unit based on the temperature inversion based VFT data.
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公开(公告)号：US20170083065A1
公开(公告)日：2017-03-23
申请号：US14862044
申请日：2015-09-22
Applicant: Advanced Micro Devices, Inc.
Inventor： Wei Huang , Manish Arora , Yasuko Eckert , Indrani Paul
CPC classification number: G06F1/206 , G06F1/3206 , G06F1/3234 , G06F1/324 , G06F1/3296 , G06F11/3024 , G06F11/3058
Abstract: A three-dimensional (3-D) processor stack includes a plurality of processor cores implemented in a plurality of layers. A controller is to selectively throttle one or more of a plurality of processor cores in response to detecting a thermal event. The controller selectively throttles the one or more of the plurality of processor cores based on values of thermal couplings between the plurality of layers and based on measures of criticality of threads executing on the plurality of processor cores.
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公开(公告)号：US20240403065A1
公开(公告)日：2024-12-05
申请号：US18680644
申请日：2024-05-31
Applicant: Advanced Micro Devices, Inc.
Inventor： Sriram Sambamurthy , Indrani Paul , Kevin M. Brandl , James R. Magro , Zhao Hui Yu , Oswin E. Housty
IPC: G06F9/4401
Abstract: The disclosed device includes multiple special purpose processors that are configured to perform, in parallel, a power on transition sequence for the device, which can involve restoring a data state of components of the device using data stored in local storages of the special purpose processors. Various other methods, systems, and computer-readable media are also disclosed.
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公开(公告)号：US20230273890A1
公开(公告)日：2023-08-31
申请号：US17682527
申请日：2022-02-28
Applicant: Advanced Micro Devices, Inc.
Inventor： Raul Gutierrez , Indrani Paul , Joseph Scanlon , Aniruddha Dasgupta , Madhusudan Chilakam
CPC classification number: G06F13/385 , G06F13/20 , G06F2213/0042
Abstract: Systems, apparatuses, and methods for a host controller inferring idleness based on activity generated by a bus-attached peripheral device are disclosed. A host controller detects activity by a first device attached to the host controller via a first bus. The host controller generates an activity vector based on the detected activity, and the host controller determines whether the activity vector indicates that the first device is only engaging in handshaking or control activity rather than data transfer. If the first device is merely communicating status information, then the host controller infers idleness and conveys an idleness indicator to a power manager. The power manager turns off power to system memory and/or other components based on the idleness indicator, but keeps enough power on to allow the host controller to communicate with the first device for handshaking or status purposes.
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Patent Agency Ranking
公开(公告)号：US20220318161A1
公开(公告)日：2022-10-06
申请号：US17219273
申请日：2021-03-31
Applicant: Advanced Micro Devices, Inc.
Inventor： Kevin M. Brandl , Indrani Paul , Jean J. Chittilappilly , Abhishek Kumar Verma , James R. Magro , Kavyashree Pilar
IPC: G06F13/16 , G06F1/3234 , G06F1/3296 , G11C11/406
Abstract: A memory controller includes a command queue and an arbiter operating in a first voltage domain, and a physical layer interface (PHY) operating in a second voltage domain. The memory controller includes isolation cells operable to isolate the PHY from the first voltage domain. A local power state controller, in response to a first power state command, provides configuration and state data for storage in an on-chip RAM memory, causes the memory controller to enter a powered-down state, and maintains the PHY in a low-power state in which the second voltage domain is powered while the memory controller is in the powered-down state.
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公开(公告)号：US11054883B2
公开(公告)日：2021-07-06
申请号：US16011476
申请日：2018-06-18
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Leonardo De Paula Rosa Piga , Samuel Naffziger , Ivan Matosevic , Indrani Paul
IPC: G06F1/324
Abstract: A power management algorithm framework proposes: 1) a Quality-of-Service (QoS) metric for throughput-based workloads; 2) heuristics to differentiate between throughput and latency sensitive workloads; and 3) an algorithm that combines the heuristic and QoS metric to determine target frequency for minimizing idle time and improving power efficiency without any performance degradation. A management algorithm framework enables optimizing power efficiency in server-class throughput-based workloads while still providing desired performance for latency sensitive workloads. The power savings are achieved by identifying workloads in which one or more cores can be run at a lower frequency (and consequently lower power) without a significant negative performance impact.
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公开(公告)号：US10048741B1
公开(公告)日：2018-08-14
申请号：US15416993
申请日：2017-01-26
Applicant: Advanced Micro Devices, Inc.
Inventor： Md Abdullah Shahneous Bari , Leonardo Piga , Indrani Paul
Abstract: Systems, apparatuses, and methods for implementing performance estimation mechanisms are disclosed. In one embodiment, a computing system includes at least one processor and a memory subsystem. During a characterization phase, the system utilizes a memory intensive workload to detect when the memory subsystem reaches its saturation point. Then, the system collects performance counter values during a sampling phase of a target application to determine the memory bandwidth. If the memory bandwidth is greater than the saturation point, then the system generates a prediction of the memory time which is based on a ratio of the memory bandwidth over the saturation point. Otherwise, if the memory bandwidth is less than the saturation point, the system assumes memory time is constant versus processor frequency. Then, the system uses the memory time and an estimate of the compute time to estimate a phase time for the target application at different processor frequencies.
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公开(公告)号：US20170371761A1
公开(公告)日：2017-12-28
申请号：US15192748
申请日：2016-06-24
Applicant: Advanced Micro Devices, Inc.
Inventor： Leonardo Piga , Brian J. Kocoloski , Wei Huang , Abhinandan Majumdar , Indrani Paul
CPC classification number: G06F11/3604 , G06F9/45516
Abstract: Systems, apparatuses, and methods for performing real-time tracking of performance targets using dynamic compilation. A performance target is specified in a service level agreement. A dynamic compiler analyzes a software application executing in real-time and determine which high-level application metrics to track. The dynamic compiler then inserts instructions into the code to increment counters associated with the metrics. A power optimization unit then utilizes the counters to determine if the system is currently meeting the performance target. If the system is exceeding the performance target, then the power optimization unit reduces the power consumption of the system while still meeting the performance target.
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公开(公告)号：US20170279703A1
公开(公告)日：2017-09-28
申请号：US15081558
申请日：2016-03-25
Applicant: Advanced Micro Devices, Inc.
Inventor： Samuel Lawrence Wasmundt , Leonardo Piga , Indrani Paul , Wei Huang , Manish Arora
CPC classification number: H04L43/16 , H04L43/08 , H04L67/10 , H04L67/1008
Abstract: Systems, apparatuses, and methods for managing variations among nodes in parallel system frameworks. Sensor and performance data associated with the nodes of a multi-node cluster may be monitored to detect variations among the nodes. A variability metric may be calculated for each node of the cluster based on the sensor and performance data associated with the node. The variability metrics may then be used by a mapper to efficiently map tasks of a parallel application to the nodes of the cluster. In one embodiment, the mapper may assign the critical tasks of the parallel application to the nodes with the lowest variability metrics. In another embodiment, the hardware of the nodes may be reconfigured so as to reduce the node-to-node variability.
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