公开(公告)号：US09110671B2

公开(公告)日：2015-08-18

申请号：US13724599

申请日：2012-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Yasuko Eckert ,  Srilatha Manne ,  William L Bircher ,  Mahdu S. S. Govindan ,  Michael J Schulte ,  Manish Arora

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/172

Abstract: A method and apparatus for exiting a low power state based on a prior prediction is disclosed. An integrated circuit (IC) includes a functional unit configured to, during operation, cycle between intervals of an active state and intervals of an idle state. The IC also include a power management unit configured to place the functional unit in a low power state responsive to the functional unit entering the idle state. The power management unit is further configured to preemptively cause the functional unit to exit the low power state at a predetermined time after entering the low power. The predetermined time is based on a prediction of idle state duration made prior to entering the low power state. The prediction may be generated by a prediction unit, based on a history of durations of intervals in which the functional unit was in the idle state.

Abstract translation: 公开了一种基于先前预测退出低功率状态的方法和装置。 集成电路（IC）包括功能单元，其被配置为在操作期间在活动状态的间隔和空闲状态的间隔之间循环。 IC还包括电源管理单元，其被配置为响应于功能单元进入空闲状态而将功能单元置于低功率状态。 电源管理单元还被配置为在进入低功率之后的预定时间，预先使功能单元退出低功率状态。 预定时间基于在进入低功率状态之前进行的空闲状态持续时间的预测。 预测可以由预测单元基于功能单元处于空闲状态的间隔的持续时间的历史来生成。

公开(公告)号：US20150186160A1

公开(公告)日：2015-07-02

申请号：US14146588

申请日：2014-01-02

Applicant: Advanced Micro Devices, Inc.

Inventor： Manish Arora ,  Indrani Paul ,  Yasuko Eckert ,  Nuwan S. Jayasena ,  Srilatha Manne

IPC: G06F9/445 ,  G06F11/34 ,  G06F12/08

CPC classification number: G06F11/3423 ,  G06F1/3243 ,  G06F11/3452 ,  G06F12/0804 ,  G06F12/0864 ,  G06F2212/601 ,  Y02D10/152 ,  Y02D10/34 ,  Y02D50/20

Abstract: Durations of active performance states of components of a processing system can be predicted based on one or more previous durations of an active state of the components. One or more entities in the processing system such as processor cores or caches can be configured based on the predicted durations of the active state of the components. Some embodiments configure a first component in a processing system based on a predicted duration of an active state of a second component of the processing system. The predicted duration is predicted based on one or more previous durations of an active state of the second component.

Abstract translation: 可以基于组件的活动状态的一个或多个先前持续时间来预测处理系统的组件的主动性能状态的持续时间。 可以基于组件的活动状态的预测持续时间来配置处理系统中的一个或多个实体，例如处理器核心或高速缓存。 一些实施例基于处理系统的第二组件的活动状态的预测持续时间来配置处理系统中的第一组件。 基于第二组件的活动状态的一个或多个先前持续时间预测预测持续时间。

公开(公告)号：US20150067266A1

公开(公告)日：2015-03-05

申请号：US14011616

申请日：2013-08-27

Applicant: Advanced Micro Devices, Inc

Inventor： Syed Ali Jafri ,  Yasuko Eckert ,  Srilatha Manne

IPC: G06F12/12

CPC classification number: G06F12/127 ,  G06F12/0804 ,  G06F12/123 ,  Y02D10/13

Abstract: A level of cache memory receives modified data from a higher level of cache memory. A set of cache lines with an index associated with the modified data is identified. The modified data is stored in the set in a cache line with an eviction priority that is at least as high as an eviction priority, before the modified data is stored, of an unmodified cache line with a highest eviction priority among unmodified cache lines in the set.

Abstract translation: 一级高速缓冲存储器从更高级别的缓存存储器接收修改的数据。 识别具有与修改的数据相关联的索引的一组高速缓存行。 修改后的数据被存储在高速缓存行中，其具有在修改数据被存储之前至少与驱逐优先级一样高的驱逐优先级，该缓存优先级在未修改的高速缓存行中具有最高驱逐优先级的未修改高速缓存行 组。

公开(公告)号：US20140297961A1

公开(公告)日：2014-10-02

申请号：US13854724

申请日：2013-04-01

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Mithuna Thottethodi ,  Yasuko Eckert ,  Srilatha Manne

IPC: G06F12/08

CPC classification number: G06F12/0875 ,  G06F12/0888 ,  G06F12/0893

Abstract: A cache memory receives a request to perform a write operation. The request specifies an address. A first determination is made that the cache memory does not include a cache line corresponding to the address. A second determination is made that the address is between a previous value of a stack pointer and a current value of the stack pointer. A third determination is made that a write history indicator is set to a specified value. The write operation is performed in the cache memory without waiting for a cache fill corresponding to the address to be performed, in response to the first, second, and third determinations.

Abstract translation: 缓存存储器接收执行写入操作的请求。 请求指定一个地址。 首先确定高速缓冲存储器不包括与该地址对应的高速缓存行。 第二个确定是地址在堆栈指针的先前值和堆栈指针的当前值之间。 第三个确定写入历史指示符被设置为指定值。 响应于第一，第二和第三确定，在高速缓冲存储器中执行写入操作，而不等待与要执行的地址相对应的高速缓存填充。

公开(公告)号：US20140181410A1

公开(公告)日：2014-06-26

申请号：US13723093

申请日：2012-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： John Kalamatianos ,  Edward J. McLellan ,  Paul Keltcher ,  Srilatha Manne ,  Richard E. Klass ,  James M. O'Connor

IPC: G06F12/12

CPC classification number: G06F12/121 ,  G06F12/0802 ,  G06F12/084 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/502 ,  G06F2212/601 ,  Y02D10/13

Abstract: In response to a processor core exiting a low-power state, a cache is set to a minimum size so that fewer than all of the cache's entries are available to store data, thus reducing the cache's power consumption. Over time, the size of the cache can be increased to account for heightened processor activity, thus ensuring that processing efficiency is not significantly impacted by a reduced cache size. In some embodiments, the cache size is increased based on a measured processor performance metric, such as an eviction rate of the cache. In some embodiments, the cache size is increased at regular intervals until a maximum size is reached.

Abstract translation: 响应处理器核心退出低功率状态，将高速缓存设置为最小大小，使得少于所有高速缓存的条目可用于存储数据，从而减少高速缓存的功耗。 随着时间的推移，可以增加高速缓存的大小以考虑到处理器活动的增加，从而确保处理效率不受减小的高速缓存大小的显着影响。 在一些实施例中，基于所测量的处理器性能度量（例如高速缓存的逐出速率）来增加高速缓存大小。 在一些实施例中，高速缓存大小以规则的间隔增加，直到达到最大大小。

公开(公告)号：US10025361B2

公开(公告)日：2018-07-17

申请号：US14297208

申请日：2014-06-05

Applicant: Advanced Micro Devices, Inc.

Inventor： Indrani Paul ,  Vignesh Trichy Ravi ,  Manish Arora ,  Srilatha Manne

IPC: G06F1/00 ,  G06F1/20 ,  G06F1/32 ,  G06F11/30 ,  G06F9/50 ,  G06F11/34

Abstract: A method includes controlling active frequency states of a plurality of heterogeneous processing units based on frequency sensitivity metrics indicating performance coupling between different types of processing units in the plurality of heterogeneous processing units. A processor includes a plurality of heterogeneous processing units and a performance controller to control active frequency states of the plurality of heterogeneous processing units based on frequency sensitivity metrics indicating performance coupling between different types of processing units in the plurality of heterogeneous processing units. The active frequency state of a first type of processing unit in the plurality of heterogeneous processing units is controlled based on a first activity metric associated with a first type of processing unit and a second activity metric associated with a second type of processing unit.

公开(公告)号：US09946319B2

公开(公告)日：2018-04-17

申请号：US14059384

申请日：2013-10-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Indrani Paul ,  Manish Arora ,  Srilatha Manne ,  William L. Bircher

IPC: G06F1/32 ,  G06F1/20

CPC classification number: G06F1/3206 ,  G06F1/206

Abstract: The described embodiments include a computing device with a first entity and a second entity. In the computing device, a management controller dynamically sets a power-state limit for the first entity based on a performance coupling and a thermal coupling between the first entity and the second entity.

公开(公告)号：US09710392B2

公开(公告)日：2017-07-18

申请号：US14460550

申请日：2014-08-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Syed Ali Jafri ,  Yasuko Eckert ,  Srilatha Manne ,  Mithuna S Thottethodi

IPC: G06F12/10 ,  G06F12/1009

CPC classification number: G06F12/1009 ,  G06F2212/1024 ,  G06F2212/654 ,  G06F2212/655 ,  G06F2212/656

Abstract: Embodiments are described for methods and systems for mapping virtual memory pages to physical memory pages by analyzing a sequence of memory-bound accesses to the virtual memory pages, determining a degree of contiguity between the accessed virtual memory pages, and mapping sets of the accessed virtual memory pages to respective single physical memory pages. Embodiments are also described for a method for increasing locality of memory accesses to DRAM in virtual memory systems by analyzing a pattern of virtual memory accesses to identify contiguity of accessed virtual memory pages, predicting contiguity of the accessed virtual memory pages based on the pattern, and mapping the identified and predicted contiguous virtual memory pages to respective single physical memory pages.

公开(公告)号：US09360918B2

公开(公告)日：2016-06-07

申请号：US13724133

申请日：2012-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Srilatha Manne ,  Sanjay Pant ,  Youngtaek Kim ,  Michael J. Schulte

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3243 ,  Y02D10/152

Abstract: A multi-core data processor includes multiple data processor cores and a circuit. The multiple data processor cores each include a power state controller having a first input for receiving an idle signal, a second input for receiving a release signal, a third input for receiving a control signal, and an output for providing a current power state. In response to the idle signal, the power state controller causes a corresponding data processor core to enter an idle state. In response to the release signal, the power state controller changes the current power state from the idle state to an active state in dependence on the control signal. The circuit is coupled to each of the multiple data processor cores for providing the control signal in response to current power states in the multiple data processor cores.

Abstract translation: 多核数据处理器包括多个数据处理器核心和一个电路。 多个数据处理器核心各自包括具有用于接收空闲信号的第一输入的功率状态控制器，用于接收释放信号的第二输入，用于接收控制信号的第三输入和用于提供当前功率状态的输出。 响应于空闲信号，电源状态控制器使相应的数据处理器核进入空闲状态。 响应于释放信号，功率状态控制器根据控制信号将当前功率状态从空闲状态改变到活动状态。 电路耦合到多个数据处理器核心中的每一个，以响应于多个数据处理器核心中的当前功率状态来提供控制信号。

公开(公告)号：US09128856B2

公开(公告)日：2015-09-08

申请号：US13854724

申请日：2013-04-01

Applicant: Advanced Micro Devices, Inc.

Inventor： Mithuna Thottethodi ,  Yasuko Eckert ,  Srilatha Manne

IPC: G06F12/08

CPC classification number: G06F12/0875 ,  G06F12/0888 ,  G06F12/0893

Abstract: A cache memory receives a request to perform a write operation. The request specifies an address. A first determination is made that the cache memory does not include a cache line corresponding to the address. A second determination is made that the address is between a previous value of a stack pointer and a current value of the stack pointer. A third determination is made that a write history indicator is set to a specified value. The write operation is performed in the cache memory without waiting for a cache fill corresponding to the address to be performed, in response to the first, second, and third determinations.

Abstract translation: 缓存存储器接收执行写入操作的请求。 请求指定一个地址。 首先确定高速缓冲存储器不包括与该地址对应的高速缓存行。 第二个确定是地址在堆栈指针的先前值和堆栈指针的当前值之间。 第三个确定写入历史指示符被设置为指定值。 响应于第一，第二和第三确定，在高速缓冲存储器中执行写入操作，而不等待与要执行的地址相对应的高速缓存填充。