公开(公告)号：US12176305B2

公开(公告)日：2024-12-24

申请号：US17676093

申请日：2022-02-18

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Pao-Nan Lee ,  Chen-Chao Wang ,  Chang Chi Lee

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/495 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/64 ,  H01L25/065

Abstract: An electronic device is disclosed. The electronic device includes a first electronic component and a power regulating structure configured to provide a first power to the first electronic component. The power regulating structure includes a first component and a second component at least partially overlapped with the first component from a top view.

公开(公告)号：US12132006B2

公开(公告)日：2024-10-29

申请号：US17566579

申请日：2021-12-30

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Pao-Nan Lee ,  Chen-Chao Wang ,  Chang Chi Lee

IPC: H01L23/31 ,  H01L23/552 ,  H01L25/16 ,  H01L49/02

CPC classification number: H01L23/552 ,  H01L23/3121 ,  H01L25/16 ,  H01L28/10 ,  H01L28/40

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes an electronic component, and an inductance component. The protection layer encapsulates the electronic component and has a top surface and a bottom surface. The top surface and the bottom surface collectively define a space to accommodate the electronic component. The inductance component outflanks the space from the top surface and the bottom surface of the protection layer.

公开(公告)号：US11901245B2

公开(公告)日：2024-02-13

申请号：US17893033

申请日：2022-08-22

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chen-Chao Wang ,  Chih-Yi Huang ,  Keng-Tuan Chang

IPC: H01L21/66 ,  H01L25/00 ,  H01L23/485 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L22/22 ,  H01L23/485 ,  H01L23/49838 ,  H01L25/0655 ,  H01L25/50

Abstract: A semiconductor package structure and a method for manufacturing the same are provided. The method includes: providing a package body includes a first semiconductor device, wherein the first semiconductor device includes a plurality of first electrical contacts disposed adjacent to an active surface of the first semiconductor device; measuring the actual positions of the first electrical contacts of the first semiconductor device; providing a plurality of second electrical contacts outside the first semiconductor device; and forming an interconnection structure based on the actual positions of the first electrical contacts of the first semiconductor device and the positions of the second electrical contacts satisfying a predetermined electrical performance criterion by a mask-less process, so as to connect the first electrical contacts and the second electrical contacts and maintain signal integrity during transmission.

公开(公告)号：US11844199B2

公开(公告)日：2023-12-12

申请号：US17585416

申请日：2022-01-26

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Li-Chieh Hung ,  Chen-Chao Wang

IPC: H05K1/18 ,  H05K7/20 ,  H05K1/02

CPC classification number: H05K7/209 ,  H05K1/0216 ,  H05K1/181

Abstract: An electronic device is disclosed. The electronic device includes a first electronic component, a first power regulator disposed above the first electronic component. The first power regulator is configured to receive a first power along a lateral surface of the first electronic component without passing the first electronic component and to provide a second power to the first electronic component. The electronic device also includes a passive component disposed in an electrical path between the first electronic component and the first power regulator.

公开(公告)号：US11733294B2

公开(公告)日：2023-08-22

申请号：US16812232

申请日：2020-03-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chen-Chao Wang ,  Tsung-Tang Tsai ,  Chih-Yi Huang

IPC: H01L23/498 ,  G01R31/28 ,  H01L23/538 ,  H01L23/552 ,  H01L25/18 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: G01R31/2896 ,  H01L23/49822 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/16 ,  H01L25/18 ,  H01L21/563 ,  H01L23/3185 ,  H01L23/3192 ,  H01L2224/16227

Abstract: A package structure and a testing method are provided. The package structure includes a wiring structure, a first electronic device and a second electronic device. The wiring structure includes at least one dielectric layer, at least one conductive circuit layer in contact with the dielectric layer, and at least one test circuit structure in contact with the dielectric layer. The test circuit structure is disposed adjacent to the interconnection portion of the conductive circuit layer. The first electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device through the interconnection portion of the conductive circuit layer.

公开(公告)号：US10903152B2

公开(公告)日：2021-01-26

申请号：US16357159

申请日：2019-03-18

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yuan-Hsi Chou ,  Tsun-Lung Hsieh ,  Chen-Chao Wang

IPC: H01L23/498 ,  H01L23/00

Abstract: A substrate includes: (1) a first patterned conductive layer, the first patterned conductive layer including a pair of first transmission lines adjacent to each other; and (2) a first reference layer above the pair of first transmission lines, the first reference layer defining an opening, wherein the pair of first transmission lines are exposed to the opening.

公开(公告)号：US10886263B2

公开(公告)日：2021-01-05

申请号：US15721257

申请日：2017-09-29

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： William T. Chen ,  John Richard Hunt ,  Chih-Pin Hung ,  Chen-Chao Wang ,  Chih-Yi Huang

IPC: H01L25/10 ,  H01L23/538 ,  H01L23/31 ,  H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L25/00 ,  H01L25/16 ,  H01L25/18 ,  H01L23/13 ,  H01L25/07 ,  H01L25/075 ,  H01L25/11 ,  H01L25/04 ,  H01L25/065

Abstract: A semiconductor device package comprises a bottom electronic device, an interposer module, a top electronic device, and a double sided redistribution layer (RDL) structure. The interposer module includes a plurality of conductive vias. The top electronic device has an active surface and is disposed above the bottom electronic device and above the interposer module. The double sided RDL structure is disposed between the bottom electronic device and the top electronic device. The active surface of the bottom electronic device faces toward the double sided RDL structure. The active surface of the top electronic device faces toward the double sided RDL structure. The double sided RDL structure electrically connects the active surface of the bottom electronic device to the active surface of the top electronic device. The double sided RDL structure electrically connects the active surface of the top electronic device to the interposer module.

公开(公告)号：US10515806B2

公开(公告)日：2019-12-24

申请号：US16297477

申请日：2019-03-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： John Richard Hunt ,  William T. Chen ,  Chih-Pin Hung ,  Chen-Chao Wang

IPC: H01L23/48 ,  H01L21/108 ,  H01L23/00 ,  H01L23/04 ,  H01L21/768 ,  H01L23/485 ,  H01L25/065 ,  H01L21/683 ,  H01L23/538 ,  H01L23/16 ,  H01L21/56 ,  H01L27/108 ,  H01L23/528 ,  H01L23/31

Abstract: A semiconductor device package includes: (1) an electronic device including an active surface and a contact pad adjacent to the active surface; and (2) a redistribution stack including a dielectric layer disposed over the active surface and defining a first opening exposing at least a portion of the contact pad; and a redistribution layer (RDL) disposed over the dielectric layer and including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending between the first portion of the first trace and the exposed portion of the contact pad, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, and the maximum width of the second portion of the first trace is no greater than 3 times of a width of the first portion of the first trace, wherein the second portion of the first trace is disposed between and spaced from opposing sidewalls of the dielectric layer defining the first opening.

公开(公告)号：US11605877B2

公开(公告)日：2023-03-14

申请号：US16544415

申请日：2019-08-19

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Sheng-Chi Hsieh ,  Chen-Chao Wang ,  Teck-Chong Lee ,  Chien-Hua Chen

IPC: H01Q1/22 ,  H01L23/498 ,  H01L23/00 ,  H01L23/66 ,  H01L23/31 ,  H01L23/552 ,  H01L21/56 ,  H01L21/48 ,  H01L23/538 ,  H01Q9/16 ,  H01L23/15

Abstract: A semiconductor device package includes a glass carrier, a package body, a first circuit layer and a first antenna layer. The glass carrier has a first surface and a second surface opposite to the first surface. The package body is disposed on the first surface of the glass carrier. The package body has an interconnection structure penetrating the package body. The first circuit layer is disposed on the package body. The first circuit layer has a redistribution layer (RDL) electrically connected to the interconnection structure of the package body. The first antenna layer is disposed on the second surface of the glass carrier.

公开(公告)号：US11515249B2

公开(公告)日：2022-11-29

申请号：US17090671

申请日：2020-11-05

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih-Yi Huang ,  Chen-Chao Wang ,  Mi-Chun Hung

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

Abstract: At least some embodiments of the present disclosure relate to a wiring structure and a method for manufacturing a wiring structure. The wiring structure includes a conductive structure, a first fan-out structure, and a second fan-out structure. The first fan-out structure is disposed on the conductive structure and includes a first circuit layer. The second fan-out structure is disposed on the conductive structure, and includes a second circuit layer. A thickness of the first circuit layer is different from a thickness of the second circuit layer.