公开(公告)号：US11257776B2

公开(公告)日：2022-02-22

申请号：US16573672

申请日：2019-09-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Sheng Lin ,  Chin-Li Kao ,  Hsu-Nan Fang

IPC: H01L25/065 ,  H01L25/16 ,  H01L25/00 ,  H01L25/18 ,  H01L23/00

Abstract: A semiconductor package structure includes a semiconductor die surface having a narrower pitch region and a wider pitch region adjacent to the narrower pitch region, a plurality of first type conductive pillars in the narrower pitch region, each of the first type conductive pillars having a copper-copper interface, and a plurality of second type conductive pillars in the wider pitch region, each of the second type conductive pillars having a copper-solder interface. A method for manufacturing the semiconductor package structure described herein is also disclosed.

公开(公告)号：US10222209B2

公开(公告)日：2019-03-05

申请号：US15862476

申请日：2018-01-04

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Seungbae Park ,  Yu-Ho Hsu ,  Chin-Li Kao ,  Tai-Yuan Huang

IPC: G01C11/02 ,  G01C11/04 ,  G01B11/245

Abstract: The measurement equipment includes a rack, a first image capturing device, a second image capturing device, a third image capturing device and a fourth image capturing device. Wherein, the first image capturing device and the second image capturing device capture an entire image of a to-be-measured object, the third image capturing device and the fourth image capturing device capture a plurality of local images of a plurality of local areas of the to-be-measured object, and the entire image and the local images and are simultaneously captured.

公开(公告)号：US10134677B1

公开(公告)日：2018-11-20

申请号：US15596956

申请日：2017-05-16

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien Lin Chang Chien ,  Chin-Li Kao ,  Shih-Yu Wang ,  Chang Chi Lee

IPC: H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/5384 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H01L2221/68345 ,  H01L2221/68359

Abstract: A semiconductor package device includes a first interconnection structure, a non-silicon interposer and a first die. The first interconnection structure has a first pitch. The non-silicon interposer surrounds the first interconnection structure. The non-silicon interposer includes a second interconnection structure having a second pitch. The second pitch is larger than the first pitch. The first die is above the first interconnection structure and is electrically connected to the first interconnection structure.

公开(公告)号：US10056325B2

公开(公告)日：2018-08-21

申请号：US15410688

申请日：2017-01-19

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chin-Li Kao ,  Chang-Chi Lee ,  Yi-Shao Lai

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/06 ,  H01L2924/07025 ,  H01L2924/15738 ,  H01L2924/15763 ,  H01L2924/15787 ,  H01L2924/15798 ,  H01L2924/3511 ,  H01L2924/35121 ,  H01L2224/0401

Abstract: The present disclosure relates to a semiconductor package and a manufacturing method thereof. The semiconductor package includes a semiconductor element including a main body, a plurality of conductive vias, and at least one filler. The conductive vias penetrate through the main body. The filler is located in the main body, and a coefficient of thermal expansion (CTE) of the filler is different from that of the main body and the conductive vias. Thus, the CTE of the overall semiconductor element can be adjusted, so as to reduce warpage.

公开(公告)号：US09891048B2

公开(公告)日：2018-02-13

申请号：US14167786

申请日：2014-01-29

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Seungbae Park ,  Yu-Ho Hsu ,  Chin-Li Kao ,  Tai-Yuan Huang

IPC: G01C11/04 ,  G01B11/245

CPC classification number: G01C11/04 ,  G01B11/245 ,  G01B2210/56

Abstract: The measurement equipment includes a rack, a first image capturing device, a second image capturing device, a third image capturing device and a fourth image capturing device. Wherein, the first image capturing device and the second image capturing device capture an entire image of a to-be-measured object, the third image capturing device and the fourth image capturing device capture a plurality of local images of a plurality of local areas of the to-be-measured object, and the entire image and the local images and are simultaneously captured.

公开(公告)号：US12113044B2

公开(公告)日：2024-10-08

申请号：US17676094

申请日：2022-02-18

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Shan-Bo Wang ,  Chin-Li Kao ,  An-Hsuan Hsu

IPC: H01L23/00 ,  H01L25/10 ,  H01L23/498

CPC classification number: H01L24/81 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L25/105 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L2224/05147 ,  H01L2224/11849 ,  H01L2224/13105 ,  H01L2224/13147 ,  H01L2224/13582 ,  H01L2224/13605 ,  H01L2224/13611 ,  H01L2224/13647 ,  H01L2224/14505 ,  H01L2224/16157 ,  H01L2224/16167 ,  H01L2224/16506 ,  H01L2224/17505 ,  H01L2224/81097 ,  H01L2224/81211 ,  H01L2224/81815 ,  H01L2224/81825 ,  H01L2224/81935 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: A semiconductor device package and a fabrication method thereof are disclosed. The semiconductor package comprises: a package component having a first mounting surface and a second mounting surface; and a first electronic component having a first conductive pad signal communicatively mounted on the first mounting surface through a first type connector; wherein the first type connector comprises a first solder composition having a lower melting point layer sandwiched between a pair of higher melting point layers, wherein the lower melting point layer is composed of alloys capable of forming a room temperature eutectic.

公开(公告)号：US11621217B2

公开(公告)日：2023-04-04

申请号：US17151062

申请日：2021-01-15

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chun-Wei Shih ,  Sheng-Wen Yang ,  Chung-Hung Lai ,  Chin-Li Kao

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/31 ,  H01L23/538

Abstract: A substrate structure and a semiconductor package structure are provided. The substrate structure includes a first dielectric layer, a pad and a conductive structure. The first dielectric layer has a first surface and a second surface opposite to the first surface. The pad is adjacent to the first surface and at least partially embedded in the first dielectric layer. The first dielectric layer has an opening exposing the pad, and a width of the opening is less than a width of the pad. The conductive structure is disposed on the pad and composed of a first portion outside the opening of the first dielectric layer and a second portion embedded in the opening of the first dielectric layer. The first portion has an aspect ratio exceeding 1.375.

公开(公告)号：US11127650B2

公开(公告)日：2021-09-21

申请号：US16799751

申请日：2020-02-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien Lin Chang Chien ,  Chiu-Wen Lee ,  Hung-Jung Tu ,  Chang Chi Lee ,  Chin-Li Kao

IPC: H01L23/36 ,  H01L21/48 ,  H01L23/48 ,  H01L23/367 ,  H01L23/00

Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a first die, a second die, and a thermal dissipation element. The first die has a first surface. The second die is disposed on the first surface. The thermal dissipation element is disposed on the first surface. The thermal dissipation element includes a first portion extending in a first direction substantially parallel to the first surface and partially covered by the second die and a second portion extending in a second direction substantially perpendicular to the first surface to be adjacent to an edge of the second die.

公开(公告)号：US11011444B2

公开(公告)日：2021-05-18

申请号：US16540837

申请日：2019-08-14

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ya-Yu Hsieh ,  Chin-Li Kao ,  Chung-Hsuan Tsai ,  Chia-Pin Chen

IPC: H01L23/29 ,  H01L23/00 ,  H01L23/31 ,  H01L21/66

Abstract: The present disclosure provides a semiconductor package structure having a semiconductor die having an active surface, a conductive bump on the active surface, configured to electrically couple the semiconductor die to an external circuit, the conductive bump having a bump height, a dielectric encapsulating the semiconductor die and the conductive bump, and a plurality of fillers in the dielectric, each of the fillers comprising a diameter, wherein a maximum diameter of the fillers is smaller than the bump height.

公开(公告)号：US10541198B2

公开(公告)日：2020-01-21

申请号：US15884197

申请日：2018-01-30

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien Lin Chang Chien ,  Chin-Li Kao ,  Chang Chi Lee ,  Chih-Pin Hung

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/00 ,  H01L23/16 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H01L21/683 ,  H01L21/48 ,  H01L23/31

Abstract: A method of manufacturing a semiconductor package includes: (a) providing a carrier; (b) disposing a dielectric layer and a conductive pad on the carrier; (c) disposing a redistribution layer on the dielectric layer to electrically connect to the conductive pad; (d) connecting a die to the redistribution layer; (e) removing at least a portion of the carrier to expose the conductive pad; and (f) disposing an electrical contact to electrically connect to the conductive pad.