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    Method to fabricate metal gate high-k devices
    11.
    发明授权
    Method to fabricate metal gate high-k devices 失效
    制造金属栅极高k器件的方法

    公开(公告)号：US07790592B2

    公开(公告)日：2010-09-07

    申请号：US11927749

    申请日：2007-10-30

    申请人： Tze-Chiang Chen ,  Bruce B. Doris ,  Vijay Narayanan ,  Vamsi Paruchuri

    发明人： Tze-Chiang Chen ,  Bruce B. Doris ,  Vijay Narayanan ,  Vamsi Paruchuri

    IPC分类号： H01L21/3205 ,  H01L21/4763 ,  H01L21/477 ,  H01L27/088

    CPC分类号： H01L21/823842 ,  H01L21/28079 ,  H01L21/823857 ,  H01L21/823878 ,  H01L29/517

    摘要： Disclosed is a method to fabricate a semiconductor device, and a device fabricated in accordance with the method. The method includes providing a substrate comprised of silicon; performing a shallow trench isolation process to delineate nFET and pFET active areas and, within each active area, forming a gate structure over a surface of the substrate, the gate structure comprising in order from the surface of the substrate, a layer of high dielectric constant oxide, a layer comprised of a metal, a layer comprised of amorphous silicon, and a layer comprised of polycrystalline silicon. The layer comprised of amorphous silicon is provided to substantially prevent regrowth of the high dielectric constant oxide layer in a vertical direction during at least a deposition and processing of the polycrystalline silicon layer and/or metal layer.

    摘要翻译： 公开了一种制造半导体器件的方法，以及根据该方法制造的器件。 该方法包括提供由硅构成的衬底; 执行浅沟槽隔离工艺以描绘nFET和pFET有源区域，并且在每个有源区域内，在衬底的表面上形成栅极结构，所述栅极结构从衬底的表面依次包括高介电常数 氧化物，由金属构成的层，由非晶硅构成的层以及由多晶硅构成的层。 提供由非晶硅组成的层，以至少在多晶硅层和/或金属层的沉积和加工过程中基本上防止高介电常数氧化物层在垂直方向上的再生长。

    Method to control flatband/threshold voltage in high-k metal gated stacks and structures thereof
    12.
    发明申请
    Method to control flatband/threshold voltage in high-k metal gated stacks and structures thereof 审中-公开
    控制高k金属栅组合中的平带/阈值电压的方法及其结构

    公开(公告)号：US20060289948A1

    公开(公告)日：2006-12-28

    申请号：US11158372

    申请日：2005-06-22

    申请人： Stephen Brown ,  Tze-Chiang Chen ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri

    发明人： Stephen Brown ,  Tze-Chiang Chen ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri

    IPC分类号： H01L29/94

    CPC分类号： H01L21/28167 ,  H01L21/28088 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/78

    摘要： The present invention provides a metal stack (or gate stack) structure that stabilizes the flatband voltage and threshold voltages of material stacks that include a gate conductor and a dielectric material having a dielectric constant of greater than about 4.0, especially a Hf-based dielectric. This present invention stabilizes the flatband voltages and the threshold voltages by introducing an alkaline earth metal-containing layer into the material stack that introduces, via electronegativity differences, a shift in the threshold voltage to the desired voltage. Specifically, the present invention provides a metal stack comprising a high k dielectric, preferably a hafnium-based dielectric; an alkaline earth metal-containing layer located atop of, or within, said high k dielectric; an electrically conductive capping layer located above said high k dielectric; and a gate conductor.

    摘要翻译： 本发明提供一种金属堆叠（或栅极堆叠）结构，其稳定包括栅极导体和介电常数大于约4.0的介电材料的材料堆叠的平带电压和阈值电压，特别是基于Hf的电介质。 本发明通过将含碱土金属的层引入材料堆中来稳定平带电压和阈值电压，其通过电负性差异将阈值电压的偏移引入所需电压。 具体地，本发明提供一种包括高k电介质，优选铪基电介质的金属叠层; 位于所述高k电介质的顶部或内部的含碱土金属的层; 位于所述高k电介质上方的导电覆盖层; 和栅极导体。

    Metal oxynitride as a pFET material
    13.
    发明申请
    Metal oxynitride as a pFET material 有权
    金属氮氧化物作为pFET材料

    公开(公告)号：US20070138578A1

    公开(公告)日：2007-06-21

    申请号：US11311455

    申请日：2005-12-19

    申请人： Alessandro Callegari ,  Michael Gribelyuk ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Sufi Zafar

    发明人： Alessandro Callegari ,  Michael Gribelyuk ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Sufi Zafar

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L21/28088 ,  H01L21/823828 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

    摘要： A compound metal comprising MOxNy which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the MOxNy compound metal. Furthermore, the MOxNy metal compound of the present invention is a very efficient oxygen diffusion barrier at 1000° C. allowing very aggressive equivalent oxide thickness (EOT) and inversion layer thickness scaling below 14 Å in a p-metal oxide semiconductor (PMOS) device. In the above formula, M is a metal selected from Group IVB, VB, VIB or VIIB of the Periodic Table of Elements, x is from about 5 to about 40 atomic % and y is from about 5 to about 40 atomic %.

    摘要翻译： 一种复合金属，其包含具有约4.75至约5.3，优选约5eV的功函数的p型金属，其在一个或多个金属上是热稳定的 提供了包括高k电介质和界面层的栅极叠层以及制造复合金属的方法。 此外，本发明的金属氧化物金属化合物在1000℃下是非常有效的氧扩散阻挡层，允许非常有效的等效氧化物厚度（EOT）和反演 在p-金属氧化物半导体（PMOS）器件中的层厚度缩小到14埃以下。 在上式中，M是选自元素周期表第IVB，VB，VIB或VIIB族的金属，x为约5至约40原子％，y为约5至约40原子％。

    Stabilization of flatband voltages and threshold voltages in hafnium oxide based silicon transistors for CMOS
    18.
    发明申请
    Stabilization of flatband voltages and threshold voltages in hafnium oxide based silicon transistors for CMOS 有权
    用于CMOS的基于铪氧化物的硅晶体管中的平带电压和阈值电压的稳定性

    公开(公告)号：US20060244035A1

    公开(公告)日：2006-11-02

    申请号：US11118521

    申请日：2005-04-29

    申请人： Nestor Bojarczuk ,  Michael Chudzik ,  Matthew Copel ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri

    发明人： Nestor Bojarczuk ,  Michael Chudzik ,  Matthew Copel ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri

    IPC分类号： H01L29/76

    CPC分类号： H01L21/28167 ,  H01L21/28185 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/517

    摘要： The present invention provides a metal stack structure that stabilizes the flatband voltage and threshold voltages of material stacks that include a Si-containing conductor and a Hf-based dielectric. This present invention stabilizes the flatband voltages and the threshold voltages by introducing a rare earth metal-containing layer into the material stack that introduces, via electronegativity differences, a shift in the threshold voltage to the desired voltage. Specifically, the present invention provides a metal stack comprising a hafnium-based dielectric; a rare earth metal-containing layer located atop of, or within, said hafnium-based dielectric; an electrically conductive capping layer located above said hafnium-based dielectric; and a Si-containing conductor.

    摘要翻译： 本发明提供一种金属堆叠结构，其稳定包括含Si导体和Hf基电介质的材料堆叠的平带电压和阈值电压。 本发明通过将含稀土金属的层引入材料堆中来稳定平带电压和阈值电压，其通过电负性差异将阈值电压的偏移引入期望的电压。 具体地说，本发明提供一种包含铪基电介质的金属叠层; 位于所述铪基电介质的顶部或内部的含稀土金属的层; 位于所述铪基电介质上方的导电覆盖层; 和含Si导体。