公开(公告)号：US07323403B2

公开(公告)日：2008-01-29

申请号：US10999271

申请日：2004-11-29

申请人： Antonio L. P. Rotondaro ,  Deborah J. Riley ,  Trace Q. Hurd

发明人： Antonio L. P. Rotondaro ,  Deborah J. Riley ,  Trace Q. Hurd

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/28088 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/32137 ,  H01L29/4966 ,  H01L29/6659

摘要： The present invention provides a method for patterning a metal gate electrode and a method for manufacturing an integrated circuit including the same. The method for patterning the metal gate electrode, among other steps, includes forming a metal gate electrode layer (220) over a gate dielectric layer (210) located on a substrate (110), and patterning the gate electrode layer (220) using a combination of a dry etch process (410) and a wet etch process (510).

摘要翻译： 本发明提供了一种图案化金属栅电极的方法和包括其的集成电路的制造方法。 除了其他步骤之外，用于图案化金属栅电极的方法包括在位于衬底（110）上的栅极电介质层（210）上形成金属栅极电极层（220），并且使用 干蚀刻工艺（410）和湿蚀刻工艺（510）的组合。

公开(公告)号：US08470707B2

公开(公告)日：2013-06-25

申请号：US13287671

申请日：2011-11-02

申请人： Weize Xiong ,  Deborah J. Riley

发明人： Weize Xiong ,  Deborah J. Riley

IPC分类号： H01L21/4763

CPC分类号： H01L21/823425 ,  H01L21/28518 ,  H01L21/823468 ,  H01L29/665 ,  H01L29/6653

摘要： A process for forming an integrated circuit with reduced sidewall spacers to enable improved silicide formation between minimum spaced transistor gates. A process for forming an integrated circuit with reduced sidewall spacers by first forming sidewall spacer by etching a sidewall dielectric and stopping on an etch stop layer, implanting source and drain dopants self aligned to the sidewall spacers, followed by removing a portion of the sidewall dielectric and removing the etch stop layer self aligned to the reduced sidewall spacers prior to forming silicide.

摘要翻译： 用于形成具有减少的侧壁间隔物的集成电路以使得能够改进最小间隔开的晶体管栅极之间的硅化物形成的工艺。 一种用于通过首先通过蚀刻侧壁电介质并停止在蚀刻停止层上形成侧壁间隔物而形成具有减小的侧壁间隔物的集成电路的工艺，将源极和漏极掺杂剂注入到与侧壁间隔物自对准，然后去除侧壁电介质的一部分 以及在形成硅化物之前去除与所述还原侧壁间隔物自对准的蚀刻停止层。

公开(公告)号：US07732284B1

公开(公告)日：2010-06-08

申请号：US12344421

申请日：2008-12-26

申请人： Brian K. Kirkpatrick ,  Jinhan Choi ,  Deborah J. Riley

发明人： Brian K. Kirkpatrick ,  Jinhan Choi ,  Deborah J. Riley

IPC分类号： H01L21/00

CPC分类号： H01L21/02071 ,  H01L21/31111 ,  H01L29/517 ,  H01L29/78 ,  Y10S438/906

摘要： A method for fabricating a CMOS integrated circuit (IC) includes the step of providing a substrate having a semiconductor surface. A gate stack including a metal gate electrode on a metal including high-k dielectric layer is formed on the semiconductor surface. Dry etching is used to pattern the gate stack to define a patterned gate electrode stack having exposed sidewalls of the metal gate electrode. The dry etching forms post etch residuals some of which are deposited on the substrate. The substrate including the patterned gate electrode stack is exposed to a solution cleaning sequence including a first clean step including a first acid and a fluoride for removing at least a portion of the post etch residuals, wherein the first clean step has a high selectivity to avoid etching the exposed sidewalls of the metal gate electrode. A second clean after the first clean consists essentially of a fluoride which removes residual high-k material on the semiconductor surface.

摘要翻译： 制造CMOS集成电路（IC）的方法包括提供具有半导体表面的衬底的步骤。 在半导体表面上形成包括金属栅电极在包含高k电介质层的金属上的栅叠层。 使用干蚀刻来图案化栅极堆叠以限定具有金属栅电极的暴露侧壁的图案化栅电极堆叠。 干蚀刻形成后蚀刻残留物，其中一些沉积在基底上。 包括图案化的栅极电极堆叠的衬底暴露于溶液清洁序列，其包括包括第一酸和氟化物的第一清洁步骤，用于去除至少一部分后蚀刻残留物，其中第一清洁步骤具有高选择性以避免 蚀刻金属栅电极的暴露的侧壁。 第一次清洁后的第二次清洁基本上由氟化物组成，其除去半导体表面上残留的高k材料。

公开(公告)号：US07569464B2

公开(公告)日：2009-08-04

申请号：US11615187

申请日：2006-12-22

申请人： Karen H. R. Kirmse ,  Yuanning Chen ,  Jarvis B. Jacobs ,  Deborah J. Riley

发明人： Karen H. R. Kirmse ,  Yuanning Chen ,  Jarvis B. Jacobs ,  Deborah J. Riley

IPC分类号： H01L21/425

CPC分类号： H01L21/823468 ,  H01L21/823418 ,  H01L21/823814 ,  H01L21/823864

摘要： The present invention provides a method for manufacturing a semiconductor device, which includes forming a gate structure over a substrate, and forming a stack of layers on the substrate and at least partially along a sidewall of the gate structure. In this embodiment, the stack of layers includes an initial layer located over the substrate, a buffer layer located over the initial layer and an offset layer located over the buffer layer. This embodiment of the method further includes removing horizontal segments of the offset layer and the buffer layer using a dry etch and a wet clean, wherein removing includes choosing at least one of an initial thickness of the buffer layer, a period of time for the dry etch or a period of time for the wet clean such that horizontal segments of the initial layer are exposed and substantially unaffected after the dry etch and wet clean.

摘要翻译： 本发明提供了一种制造半导体器件的方法，其包括在衬底上形成栅极结构，并且在衬底上至少部分地沿着栅极结构的侧壁形成层叠层。 在该实施例中，层叠层包括位于衬底上的初始层，位于初始层之上的缓冲层和位于缓冲层上方的偏移层。 该方法的该实施例还包括使用干蚀刻和湿清洁来去除偏移层和缓冲层的水平段，其中移除包括选择缓冲层的初始厚度中的至少一个，干燥时间 蚀刻或湿式清洁的时间段，使得初始层的水平段在干蚀刻和湿清洁之后暴露并基本上不受影响。

公开(公告)号：US07384869B2

公开(公告)日：2008-06-10

申请号：US11100530

申请日：2005-04-07

申请人： Deborah J. Riley ,  Brian M. Trentman ,  Brian K. Kirkpatrick

发明人： Deborah J. Riley ,  Brian M. Trentman ,  Brian K. Kirkpatrick

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/32139 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/28035 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31662 ,  H01L21/32 ,  H01L21/76224

摘要： A method for protecting exposed silicon from attack by phosphoric acid during wet etching and stripping processes is provided. According to various embodiments of the method, a thick chemical oxide layer can be formed on the exposed silicon to protect the exposed portion from etching by phosphoric acid. The method can include exposing the silicon to at least one of a hot ozonated sulfuric acid and a hot peroxide sulfuric acid to form the thick chemical oxide.

摘要翻译： 提供了一种在湿蚀刻和剥离过程中保护暴露的硅免受磷酸侵蚀的方法。 根据该方法的各种实施例，可以在暴露的硅上形成厚的化学氧化物层，以保护暴露部分免受磷酸腐蚀。 该方法可以包括将硅暴露于热臭氧化硫酸和热过氧化硫酸中的至少一种以形成厚的化学氧化物。

公开(公告)号：US07132365B2

公开(公告)日：2006-11-07

申请号：US10914928

申请日：2004-08-10

申请人： Sue Ellen Crank ,  Shirin Siddiqui ,  Deborah J. Riley ,  Trace Quentin Hurd ,  Peijun J. Chen

发明人： Sue Ellen Crank ,  Shirin Siddiqui ,  Deborah J. Riley ,  Trace Quentin Hurd ,  Peijun J. Chen

IPC分类号： H01L21/4763

CPC分类号： H01L21/28518 ,  H01L21/76829

摘要： A method of preparing a die comprises treating exposed silicon to form an oxide prior to silicide formation; and depositing metal on the oxide. The metal may comprise titanium, cobalt, nickel, platinum, palladium, tungsten, molybdenum, or combinations thereof on the oxide. The oxide may be less than or equal to about 15 angstroms thick. In various embodiments, treating exposed silicon to form an oxide comprises forming a non-thermal oxide. Treating exposed silicon to form an oxide may also comprise treating the exposed silicon with an oxidizing plasma; alternatively, treating exposed silicon to form an oxide may comprise forming a chemical oxide. In certain other embodiments, treating exposed silicon to form an oxide comprises treating exposed silicon with a solution comprising ammonium hydroxide, hydrogen peroxide, and water; hydrochloric acid, hydrogen peroxide, and water; hydrogen peroxide; ozone; ozonated deionized water; or combinations thereof.

摘要翻译： 制备模具的方法包括在硅化物形成之前处理暴露的硅以形成氧化物; 并在氧化物上沉积金属。 金属可以在氧化物上包含钛，钴，镍，铂，钯，钨，钼或其组合。 氧化物可以小于或等于约15埃厚。 在各种实施方案中，处理暴露的硅以形成氧化物包括形成非热氧化物。 处理暴露的硅以形成氧化物还可以包括用氧化等离子体处理暴露的硅; 或者，处理暴露的硅以形成氧化物可包括形成化学氧化物。 在某些其他实施方案中，处理暴露的硅以形成氧化物包括用包含氢氧化铵，过氧化氢和水的溶液处理暴露的硅; 盐酸，过氧化氢和水; 过氧化氢; 臭氧; 臭氧化去离子水; 或其组合。

公开(公告)号：US07098099B1

公开(公告)日：2006-08-29

申请号：US11064583

申请日：2005-02-24

申请人： Brian E. Hornung ,  Jong Yoon ,  Deborah J. Riley ,  Amitava Chatterjee

发明人： Brian E. Hornung ,  Jong Yoon ,  Deborah J. Riley ,  Amitava Chatterjee

IPC分类号： H01L21/8238

CPC分类号： H01L21/823864 ,  H01L21/823814

摘要： The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). In one embodiment, the method includes growing an oxide layer 120 from a substrate 104, 106 over a first dopant region 122 and a second dopant region 128, implanting a first dopant through the oxide layer 120, into the substrate 104 in the first dopant region 122, and adjacent a gate structure 114, and substantially removing the oxide layer 120 from the substrate within the second dopant region 128. Subsequent to the removal of the oxide layer 120 in the second dopant region 128, a second dopant that is opposite in type to the first dopant is implanted into the substrate 106 and within the second dopant region 128 and adjacent a gate structure 114.

摘要翻译： 本发明在一个实施例中提供一种制造半导体器件（100）的方法。 在一个实施例中，该方法包括在第一掺杂剂区域122和第二掺杂剂区域128之上从衬底104,106生长氧化物层120，将第一掺杂剂注入到氧化物层120中，将第一掺杂剂注入第一掺杂剂区域 并且与栅极结构114相邻，并且在第二掺杂剂区域128内基本上从衬底去除氧化物层120。 在第二掺杂区域128中除去氧化物层120之后，将与第一掺杂剂类型相反的第二掺杂剂注入到衬底106中并且在第二掺杂剂区域128内并且与栅极结构114相邻。

公开(公告)号：US20100032813A1

公开(公告)日：2010-02-11

申请号：US12538280

申请日：2009-08-10

申请人： Deborah J. Riley ,  Haowen Bu ,  Brian Edward Hornung

发明人： Deborah J. Riley ,  Haowen Bu ,  Brian Edward Hornung

IPC分类号： H01L23/29 ,  H01L21/31

CPC分类号： H01L21/02238 ,  H01L21/02164 ,  H01L21/02255 ,  H01L21/31654 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/7833

摘要： A semiconductor device, such as an integrated circuit, has an oxide chemically grown on a silicon surface, and densified by annealing at, e.g., 950° C. for 4 to 5 seconds in an N2 ambient, or at an equivalent thermal profile in a similarly non-oxidizing ambient. The densified chemical oxide has an etch rate the same as that of thermally grown silicon dioxide in common etchants used in IC fabrication.

摘要翻译： 诸如集成电路的半导体器件具有在硅表面上化学生长的氧化物，并且通过在例如950℃下在N 2环境中退火4至5秒或在等温热分布中致密化 类似的非氧化环境。 致密化学氧化物的蚀刻速率与用于IC制造的常用蚀刻剂中的热生长二氧化硅的蚀刻速率相同。

公开(公告)号：US07537988B2

公开(公告)日：2009-05-26

申请号：US11870241

申请日：2007-10-10

申请人： Shashank Ekbote ,  Deborah J. Riley ,  Borna Obradovic

发明人： Shashank Ekbote ,  Deborah J. Riley ,  Borna Obradovic

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L21/823864 ,  H01L27/11

摘要： A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric and a plurality of gate electrodes thereon in both NMOS and PMOS regions using the surface. A multi-layer offset spacer stack including a top layer and a compositionally different bottom layer is formed and the multi-layer spacer stack is etched to form offset spacers on sidewalls of the gate electrodes. The transistors designed to utilize a thinner offset spacer are covered with a first masking material, and transistors designed to utilize a thicker offset spacer are patterned and first implanted. At least a portion of the top layer is removed to leave the thinner offset spacers on sidewalls of the gate electrodes. The transistors designed to utilize the thicker offset spacer are covered with a second masking material, and the transistors designed to utilize the thinner offset spacer are patterned and second implanted. The fabrication of the integrated circuit is then completed.

摘要翻译： 制造CMOS集成电路的方法包括以下步骤：使用该表面在NMOS和PMOS区域中提供具有半导体表面的衬底，在其上形成栅极电介质和多个栅电极。 形成包括顶层和组成不同底层的多层偏移间隔堆叠，并且蚀刻多层间隔堆叠以在栅电极的侧壁上形成偏置间隔物。 设计成利用较薄的偏移间隔物的晶体管被​​第一掩模材料覆盖，并且被设计成利用更厚的偏移间隔物的晶体管被​​图案化并且首先被注入。 去除顶层的至少一部分以在栅电极的侧壁上留下较薄的偏移间隔物。 设计成利用较厚的偏移间隔物的晶体管被​​第二掩模材料覆盖，并且设计成利用较薄的偏移间隔物的晶体管被​​图案化并且被第二次注入。 然后完成集成电路的制造。

公开(公告)号：US07371691B2

公开(公告)日：2008-05-13

申请号：US10901827

申请日：2004-07-29

申请人： Lindsey H. Hall ,  Trace Q. Hurd ,  Deborah J. Riley

发明人： Lindsey H. Hall ,  Trace Q. Hurd ,  Deborah J. Riley

IPC分类号： H01L21/3065

CPC分类号： H01L21/31138 ,  G03F7/423 ,  G03F7/427 ,  H01L21/31133 ,  H01L21/8238 ,  H01L29/6659

摘要： The present invention provides a process of manufacturing a semiconductor device 200 while reducing silicon loss. In one aspect, the process includes removing a photoresist layer 270 from a semiconductor substrate 235 adjacent a gate 240 and cleaning the semiconductor substrate with a wet clean solution. The removing step includes subjecting the photoresist layer 270 to a plasma ash. The plasma ash removes at least a portion of a crust 275 formed on the photoresist layer 270 but leaves a substantial portion of the photoresist layer 270. The photoresist layer 270 is subjected to a wet etch subsequent to the plasma ash that removes a substantial portion of the photoresist layer 270.

摘要翻译： 本发明提供一种在减少硅损耗的同时制造半导体器件200的工艺。 在一个方面，该方法包括从邻近门240的半导体衬底235去除光致抗蚀剂层270并用湿清洁溶液清洁半导体衬底。 去除步骤包括使光致抗蚀剂层270经受等离子体灰分。 等离子体灰去除形成在光致抗蚀剂层270上的外壳275的至少一部分，但留下光致抗蚀剂层270的大部分。 光致抗蚀剂层270在等离子体灰之后进行湿法蚀刻，其除去光致抗蚀剂层270的主要部分。