公开(公告)号：US10746696B2

公开(公告)日：2020-08-18

申请号：US15383415

申请日：2016-12-19

Applicant: Analog Devices, Inc.

Inventor： Chen Yang ,  Yumeng Liu ,  Li Chen ,  Kuang L. Yang

IPC: G01N27/447

Abstract: A microfluidic ion detector for detecting heavy metal ions in liquid and particulate matter from gas samples is described. The microfluidic ion detector includes a sample extraction structure for extracting sample ions from a sample liquid or extracting sample ions from the particulate matter of a gas sample, a separation structure for separating sample ions of different types once extracted, and a detection structure for detecting the sample ions. The microfluidic ion detector also includes a reference reservoir providing a reference ion against which the sample may be calibrated based on the operation of the separation structure. A portable, self-calibrating ion detector may be realized by including the described components on a single substrate.

公开(公告)号：US09764946B2

公开(公告)日：2017-09-19

申请号：US14062157

申请日：2013-10-24

Applicant: Analog Devices, Inc.

Inventor： Li Chen ,  Thomas Kieran Nunan ,  Kuang L. Yang

IPC: H01L29/84 ,  B81B7/00 ,  B81B3/00 ,  B81C1/00 ,  B81C3/00

CPC classification number: B81B7/0035 ,  B81B3/0094 ,  B81B7/0041 ,  B81B2201/0235 ,  B81B2207/012 ,  B81B2207/095 ,  B81C1/00293 ,  B81C3/001 ,  B81C2203/019

Abstract: A capped micromachined device has a movable micromachined structure in a first hermetic chamber and one or more interconnections in a second hermetic chamber that is hermetically isolated from the first hermetic chamber, and a barrier layer on its cap where the cap faces the first hermetic chamber, such that the first hermetic chamber is isolated from outgassing from the cap.

公开(公告)号：US11097942B2

公开(公告)日：2021-08-24

申请号：US15334619

申请日：2016-10-26

Applicant: Analog Devices, Inc.

Inventor： Thomas Kieran Nunan ,  Li Chen

IPC: B81B7/00 ,  B81C1/00 ,  B81C3/00 ,  H01L21/768 ,  H01L23/48

Abstract: Integrated circuit substrates having through silicon vias (TSVs) are described. The TSVs are vias extending through the silicon substrate in which the integrated circuitry is formed. The TSVs may be formed prior to formation of the integrated circuitry on the integrated circuit substrate, allowing the use of via materials which can be fabricated at relatively small sizes. The integrated circuit substrates may be bonded with a substrate having a microelectromechanical systems (MEMS) device. In some such situations, the circuitry of the integrated circuit substrate may face away from the MEMS substrate since the TSVs may provide electrical connection from the circuitry side of the integrated circuit substrate to the MEMS device.

公开(公告)号：US10081535B2

公开(公告)日：2018-09-25

申请号：US13926384

申请日：2013-06-25

Applicant: Analog Devices, Inc.

Inventor： Li Chen ,  Thomas Kieran Nunan ,  Kuang L. Yang ,  Jeffrey A. Gregory

IPC: B81B7/00 ,  B81C1/00 ,  H01L21/02 ,  H01L25/065

CPC classification number: B81B7/0029 ,  B81C1/00238 ,  B81C1/00349 ,  H01L21/02126 ,  H01L25/0657 ,  H01L2224/81801 ,  H01L2924/10253 ,  H01L2924/1461

Abstract: One or more conductive shielding plates are formed in a standard ASIC wafer top metal layer, e.g., for blocking cross-talk from MEMS device structure(s) on the MEMS wafer to circuitry on the ASIC wafer when the MEMS device is capped directly by the ASIC wafer in a wafer-level chip scale package. Generally speaking, a shielding plate should be at least slightly larger than the MEMS device structure it is shielding (e.g., a movable MEMS structure such as an accelerometer proof mass or a gyroscope resonator), and the shielding plate cannot be in contact with the MEMS device structure during or after wafer bonding. Thus, a recess is formed to ensure that there is sufficient cavity space away from the top surface of the MEMS device structure. The shielding plate is electrically conductive and can be biased, e.g., to the same voltage as the opposing MEMS device structure in order to maintain zero electrostatic attraction force between the MEMS device structure and the shielding plate.

公开(公告)号：US20180111823A1

公开(公告)日：2018-04-26

申请号：US15334619

申请日：2016-10-26

Applicant: Analog Devices, Inc.

Inventor： Thomas Kieran Nunan ,  Li Chen

IPC: B81B7/00 ,  H01L21/768 ,  B81C3/00 ,  H01L23/48

CPC classification number: B81B7/0006 ,  B81B2201/0228 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/0264 ,  B81B2203/0315 ,  B81B2207/012 ,  B81B2207/07 ,  B81B2207/096 ,  B81C1/00238 ,  B81C3/001 ,  B81C2203/036 ,  B81C2203/037 ,  B81C2203/0792 ,  H01L21/76898 ,  H01L23/481

Abstract: Integrated circuit substrates having through silicon vias (TSVs) are described. The TSVs are vias extending through the silicon substrate in which the integrated circuitry is formed. The TSVs may be formed prior to formation of the integrated circuitry on the integrated circuit substrate, allowing the use of via materials which can be fabricated at relatively small sizes. The integrated circuit substrates may be bonded with a substrate having a microelectromechanical systems (MEMS) device. In some such situations, the circuitry of the integrated circuit substrate may face away from the MEMS substrate since the TSVs may provide electrical connection from the circuitry side of the integrated circuit substrate to the MEMS device.

公开(公告)号：US09556017B2

公开(公告)日：2017-01-31

申请号：US13926257

申请日：2013-06-25

Applicant: Analog Devices, Inc.

Inventor： Li Chen ,  Thomas Kieran Nunan ,  Kuang L. Yang

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B3/0051 ,  B81B3/0005 ,  B81B3/0059 ,  B81B2207/012 ,  B81C1/00976 ,  B81C2201/112 ,  B81C2203/0118

Abstract: One or more stopper features (e.g., bump structures) are formed in a standard ASIC wafer top passivation layer for preventing MEMS device stiction vertically in integrated devices having a MEMS device capped directly by an ASIC wafer. A TiN coating may be used on the stopper feature(s) for anti-stiction. An electrical potential may be applied to the TiN anti-stiction coating of one or more stopper features.

Abstract translation: 在标准ASIC晶片顶部钝化层中形成一个或多个塞子特征（例如，凸起结构），用于在具有由ASIC晶片直接覆盖的MEMS器件的集成器件中垂直地防止MEMS器件静电。 TiN涂层可用于阻塞特征以用于抗静电。 可以将电势施加到一个或多个塞子特征的TiN抗静电涂层。

公开(公告)号：US20150097253A1

公开(公告)日：2015-04-09

申请号：US14045855

申请日：2013-10-04

Applicant: Analog Devices, Inc.

Inventor： Christine H. Tsau ,  Li Chen ,  Kuang L. Yang

IPC: B81B7/00 ,  B81C1/00 ,  H01L29/84

CPC classification number: B81B7/0038 ,  B81B2201/0235 ,  B81B2201/0242 ,  G01P1/023 ,  G01P15/0802 ,  H01L29/84

Abstract: A MEMS apparatus has a substrate, a cap forming first and second chambers with the base, and movable microstructure within the first and second chambers. To control pressures, the MEMS apparatus also has a first outgas structure within the first chamber. The first outgas structure produces a first pressure within the first chamber, which is isolated from the second chamber, which, like the first chamber, has a second pressure. The first pressure is different from that in the second pressure (e.g., a higher pressure or lower pressure).

Abstract translation: MEMS装置具有基板，形成具有基座的第一和第二室的盖以及第一和第二室内的可移动微结构。 为了控制压力，MEMS装置还在第一室内具有第一排气结构。 第一排气结构在第一室内产生第一压力，该第一压力与第二室隔离，其与第一室相似，具有第二压力。 第一压力与第二压力（例如，较高压力或更低压力）不同。

公开(公告)号：US08921128B2

公开(公告)日：2014-12-30

申请号：US13904681

申请日：2013-05-29

Applicant: Analog Devices, Inc.

Inventor： Li Chen ,  Kuang L. Yang

IPC: B81C1/00 ,  H01L21/66

CPC classification number: B81C99/0045

Abstract: Manufactured capped MEMS device wafers are tested for hermeticity on a vacuum prober at differing pressures or on a wafer prober at differing temperatures. Resonant frequency testing is conducted. Leaking MEMS devices are distinguished from the remaining MEMS devices on the basis of quality factor (“Q”) measurements obtained from the resonant frequency testing.

Abstract translation: 在不同压力下或在不同温度下的晶圆探测器上对制造的封装的MEMS器件晶片进行真空探测器的气密性测试。 进行谐振频率测试。 基于从谐振频率测试获得的品质因数（“Q”）测量，泄漏的MEMS器件与剩余的MEMS器件不同。

公开(公告)号：US20140356989A1

公开(公告)日：2014-12-04

申请号：US13904681

申请日：2013-05-29

Applicant: Analog Devices, Inc.

Inventor： Li Chen ,  Kuang L. Yang

IPC: B81C1/00 ,  H01L21/66

CPC classification number: B81C99/0045

Abstract: Manufactured capped MEMS device wafers are tested for hermeticity on a vacuum prober at differing pressures or on a wafer prober at differing temperatures. Resonant frequency testing is conducted. Leaking MEMS devices are distinguished from the remaining MEMS devices on the basis of quality factor (“Q”) measurements obtained from the resonant frequency testing.

Abstract translation: 在不同压力下或在不同温度下的晶圆探测器上对制造的封装的MEMS器件晶片进行真空探测器的气密性测试。 进行谐振频率测试。 基于从谐振频率测试获得的品质因数（“Q”）测量，泄漏的MEMS器件与剩余的MEMS器件不同。

公开(公告)号：US20140332945A1

公开(公告)日：2014-11-13

申请号：US14338754

申请日：2014-07-23

Applicant: Analog Devices, Inc.

Inventor： Li Chen ,  Mitul Dalal

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00269 ,  B81B7/0058 ,  B81C1/00333 ,  B81C1/00523 ,  B81C2203/0118 ,  H01L21/4803 ,  H01L21/50 ,  H01L23/04 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of etching a plurality of cavities in a wafer provides a wafer having a patterned hard mask layer. The patterned hard mask has open areas defining locations for first cavities and second cavities. A mask is applied to cover the patterned hard mask layer. The mask is etched to remove wafer material from areas defined by the second cavities. The mask is removed and etching then removes wafer material except as prevented by the hard mask layer. This leaves the first cavities with a first depth and further deepens the second cavities to a depth greater than the first depth. By suitably configuring the second cavities, a capped die can be formed by securing the wafer to a second wafer and removing at least a portion of the unsecured side of the first wafer to expose the second cavities, thereby forming a plurality of caps on the second wafer.

Abstract translation: 蚀刻晶片中的多个空腔的方法提供具有图案化硬掩模层的晶片。 图案化的硬掩模具有限定第一腔和第二腔的位置的开放区域。 施加掩模以覆盖图案化的硬掩模层。 蚀刻掩模以从由第二腔限定的区域中去除晶片材料。 除去掩模，然后蚀刻除去硬掩模层所防止的晶片材料。 这使得第一空腔具有第一深度并且进一步将第二空腔加深至大于第一深度的深度。 通过适当地构造第二空腔，可以通过将晶片固定到第二晶片并且移除第一晶片的不安全侧的至少一部分以暴露第二空腔来形成封盖的裸片，由此在第二晶圆上形成多个盖 晶圆。