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    Integrated circuit having pairs of parallel complementary FinFETs
    11.
    发明授权
    Integrated circuit having pairs of parallel complementary FinFETs 失效
    具有成对的并联互补FinFET的集成电路

    公开(公告)号：US07517806B2

    公开(公告)日：2009-04-14

    申请号：US11186748

    申请日：2005-07-21

    Applicant: Andres Bryant ,  William F. Clark, Jr. ,  David M. Fried ,  Mark D. Jaffe ,  Edward J. Nowak ,  John J. Pekarik ,  Christopher S. Putnam

    Inventor： Andres Bryant ,  William F. Clark, Jr. ,  David M. Fried ,  Mark D. Jaffe ,  Edward J. Nowak ,  John J. Pekarik ,  Christopher S. Putnam

    IPC: H01L21/302

    CPC classification number: H01L21/84 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/823821 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/785 ,  Y10S438/947

    Abstract: A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin, and a second-type of FinFET which includes a second fin running parallel to the first fin. The invention also has an insulator fin positioned between the source/drain regions of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin and the second fin, such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET. The differences between the first impurity doping region and the second impurity doping region provide the gate with different work functions related to differences between the first-type of FinFET and the second-type of FinFET. The first fin and the second fin have approximately the same width.

    Abstract translation: 公开了利用互补翅片型场效应晶体管（FinFET）的集成电路结构的方法和结构。 本发明具有包括第一鳍片的第一类型的FinFET和包括与第一鳍片平行的第二鳍片的第二类型的FinFET。 本发明还具有位于第一第一类型FinFET的源极/漏极区域和第二类型FinFET之间的绝缘体鳍片。 绝缘体鳍片具有与第一鳍片和第二鳍片大致相同的宽度尺寸，使得第一类型的FinFET和第二类型的FinFET之间的间隔大致等于一个鳍片的宽度。 本发明还具有形成在第一类型FinFET和第二类型FinFET的沟道区上的公共栅极。 栅极包括与第一类型的FinFET相邻的第一杂质掺杂区域和与第二类型的FinFET相邻的第二杂质掺杂区域。 第一杂质掺杂区域和第二杂质掺杂区域之间的差异为栅极提供与第一类型FinFET和第二类型FinFET之间的差异有关的不同功函数。 第一鳍片和第二鳍片具有大致相同的宽度。

    Pixel sensor cell for collecting electrons and holes
    13.
    发明授权
    Pixel sensor cell for collecting electrons and holes 有权
    用于收集电子和空穴的像素传感器单元

    公开(公告)号：US07977711B2

    公开(公告)日：2011-07-12

    申请号：US12172305

    申请日：2008-07-14

    Applicant: James W. Adkisson ,  Andres Bryant ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Jeffrey B. Johnson ,  Alain Loiseau

    Inventor： James W. Adkisson ,  Andres Bryant ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Jeffrey B. Johnson ,  Alain Loiseau

    IPC: H01L27/148 ,  H01L31/062

    CPC classification number: H01L27/14603 ,  H01L27/14609 ,  H01L27/14689 ,  H01L31/035281

    Abstract: The present invention is a pixel sensor cell and method of making the same. The pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a pixel sensor cell circuit. A pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input.

    Abstract translation: 本发明是像素传感器单元及其制造方法。 像素传感器单元对于给定的光量大约使可用信号加倍。 本发明的器件利用通过在像素传感器单元电路中照射光子而产生的空穴。 具有降低的复杂度的像素传感器单元包括形成在基板的表面下面的n型收集阱区域，用于收集由电子辐射照射在像素传感器单元上​​产生的电子以及形成在基板表面下方的p型收集阱区域 用于收集由撞击光子产生的孔。 具有第一输入的电路结构耦合到n型收集阱区域，而第二输入端耦合到p型收集阱区域，其中像素传感器单元的输出信号是信号的差值的大小 的第一输入和第二输入的信号。

    ISOLATION WITH OFFSET DEEP WELL IMPLANTS
    14.
    发明申请
    ISOLATION WITH OFFSET DEEP WELL IMPLANTS 有权
    隔离深度较深的植入物

    公开(公告)号：US20100289082A1

    公开(公告)日：2010-11-18

    申请号：US12464206

    申请日：2009-05-12

    Applicant: James W. Adkisson ,  Andres Bryant ,  Mark D. Jaffe ,  Alain Loiseau

    Inventor： James W. Adkisson ,  Andres Bryant ,  Mark D. Jaffe ,  Alain Loiseau

    IPC: H01L27/088 ,  H01L21/266 ,  H01L21/8234

    CPC classification number: H01L29/1083 ,  H01L21/26513 ,  H01L21/823892

    Abstract: A method implants impurities into well regions of transistors. The method prepares a first mask over a substrate and performs a first shallow well implant through the first mask to implant first-type impurities to a first depth of the substrate. The first mask is removed and a second mask is prepared over the substrate. The method performs a second shallow well implant through the second mask to implant second-type impurities to the first depth of the substrate and then removes the second mask. A third mask is prepared over the substrate. The third mask has openings smaller than openings in the first mask and the second mask. A first deep well implant is performed through the third mask to implant the first-type impurities to a second depth of the substrate, the second depth of the substrate being greater than the first depth of the substrate. The third mask is removed and a fourth mask is prepared over the substrate, the fourth mask has openings smaller than the openings in the first mask and the second mask. Then, a second deep well implant is performed through the fourth mask to implant the second-type impurities to the second depth of the substrate.

    Abstract translation: 一种方法是将杂质掺入晶体管的阱区。 该方法在衬底上制备第一掩模，并且通过第一掩模执行第一浅阱注入，以将第一类型杂质注入到衬底的第一深度。 去除第一个掩模，并在衬底上制备第二个掩模。 该方法通过第二掩模执行第二浅井注入，以将第二类型杂质植入衬底的第一深度，然后移除第二掩模。 在衬底上制备第三个掩模。 第三掩模具有比第一掩模和第二掩模中的开口小的开口。 通过第三掩模执行第一深孔注入，以将第一类型的杂质注入衬底的第二深度，衬底的第二深度大于衬底的第一深度。 去除第三掩模并在衬底上制备第四掩模，第四掩模具有小于第一掩模和第二掩模中的开口的开口。 然后，通过第四掩模进行第二深孔注入，以将第二类型的杂质植入到衬底的第二深度。

    PIXEL SENSOR CELL FOR COLLECTING ELECTRONS AND HOLES
    16.
    发明申请
    PIXEL SENSOR CELL FOR COLLECTING ELECTRONS AND HOLES 有权
    用于收集电子和孔的像素传感器单元

    公开(公告)号：US20080272400A1

    公开(公告)日：2008-11-06

    申请号：US12172309

    申请日：2008-07-14

    Applicant: James W. Adkisson ,  Andres Bryant ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Jeffrey B. Johnson ,  Alain Loiseau

    Inventor： James W. Adkisson ,  Andres Bryant ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Jeffrey B. Johnson ,  Alain Loiseau

    IPC: H01L31/00

    CPC classification number: H01L27/14603 ,  H01L27/14609 ,  H01L27/14689 ,  H01L31/035281

    Abstract: The present invention is a pixel sensor cell and method of making the same. The pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a pixel sensor cell circuit. A pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input.

    Abstract translation: 本发明是像素传感器单元及其制造方法。 像素传感器单元对于给定的光量大约使可用信号加倍。 本发明的器件利用通过在像素传感器单元电路中照射光子而产生的空穴。 具有降低的复杂度的像素传感器单元包括形成在基板的表面下面的n型收集阱区域，用于收集由电子辐射照射在像素传感器单元上​​产生的电子以及形成在基板表面下方的p型收集阱区域 用于收集由撞击光子产生的孔。 具有第一输入的电路结构耦合到n型收集阱区域，而第二输入端耦合到p型收集阱区域，其中像素传感器单元的输出信号是信号的差值的大小 的第一输入和第二输入的信号。

    Transistor structure with thick recessed source/drain structures and fabrication process of same
    18.
    发明授权
    Transistor structure with thick recessed source/drain structures and fabrication process of same 失效
    晶体管结构具有较厚的凹陷源/漏极结构及其制造工艺

    公开(公告)号：US06870225B2

    公开(公告)日：2005-03-22

    申请号：US09682957

    申请日：2001-11-02

    Applicant: Andres Bryant ,  Mark D. Jaffe

    Inventor： Andres Bryant ,  Mark D. Jaffe

    IPC: H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L27/01 ,  H01L31/0392

    CPC classification number: H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66772 ,  H01L29/66795

    Abstract: An improved transistor structure that decreases source/drain (S/D) resistance without increasing gate-to-S/D capacitance, thereby increasing device operation. S/D structures are formed into recesses formed on a semiconductor wafer through a semiconductor layer and a first layer of a buried insulator having at least two layers. A body is formed from the semiconductor layer situated between the recesses, and the body comprises a top body surface and a bottom body surface that define a body thickness. Top portions of the S/D structures are within and abut the body thickness. An improved method for forming the improved transistor structure is also described and comprises: forming recesses through a semiconductor layer and a first layer of a buried insulator so that a body is situated between the recesses; and forming S/D structures into the recesses so that top portions of the S/D structures are within and abut a body thickness.

    Abstract translation: 一种改进的晶体管结构，可在不增加栅极至S / D电容的情况下降低源/漏（S / D）电阻，从而增加器件工作。 S / D结构通过半导体层形成在半导体晶片上形成的凹槽和具有至少两层的埋入式绝缘体的第一层。 由位于凹部之间的半导体层形成主体，并且主体包括限定主体厚度的顶部主体表面和底部主体表面。 S / D结构的顶部在体厚之内并与之相邻。 还描述了用于形成改进的晶体管结构的改进方法，并且包括：通过半导体层和埋入绝缘体的第一层形成凹槽，使得主体位于凹部之间; 并且将S / D结构形成到凹部中，使得S / D结构的顶部部分在主体厚度之内并且抵接在本体的厚度上。

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