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公开(公告)号：US20150371607A1
公开(公告)日：2015-12-24
申请号：US14309645
申请日：2014-06-19
Applicant: Apple Inc.
Inventor： Peter F. Holland , Brijesh Tripathi , Dinesh M. Shedge
CPC classification number: G06T1/60 , G06F3/1438 , G06T1/20 , G09G5/399 , G09G2310/0221 , G09G2352/00 , G09G2360/06
Abstract: Systems, apparatuses, and methods for driving a split display with multiple display pipelines. Frames for driving a display are logically divided into portions, a first display pipeline drives a first portion of the display, and a second display pipeline drives a second portion of the display. To ensure synchronization between the two display pipelines, a repeat vertical blanking interval (VBI) signal is generated if either of the display pipelines has not already received the frame packet with configuration data for the next frame. When the repeat VBI signal is generated, both display pipelines will repeat processing of the current frame.
Abstract translation: 用多个显示管道驱动分割显示的系统，设备和方法。 用于驱动显示器的框架被逻辑地分为多个部分，第一显示管道驱动显示器的第一部分，第二显示管线驱动显示器的第二部分。 为了确保两个显示管道之间的同步，如果显示管道中的任一个还没有接收到具有下一帧的配置数据的帧分组，则生成重复垂直消隐间隔（VBI）信号。 当产生重复VBI信号时，两条显示管道将重复对当前帧的处理。
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公开(公告)号：US20150213780A1
公开(公告)日：2015-07-30
申请号：US14683240
申请日：2015-04-10
Applicant: Apple Inc.
Inventor： Brijesh Tripathi
CPC classification number: G09G5/008 , G06T1/20 , G06T2200/28 , G09G3/2096 , G09G5/003 , G09G5/006 , G09G5/12 , G09G5/363 , G09G2320/103 , G09G2330/02 , G09G2360/18 , G09G2370/04 , G09G2370/10 , G09G2370/12 , H04J3/0667 , H04N21/4302 , H04N21/4305
Abstract: Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The sink processor may be operable to send a synchronization signal to the source processor through the interface. The source processor may be operable, dependent upon the synchronization signal, to send data to the sink processor.
Abstract translation: 公开了一种用于实现显示端口接口的设备的实施例。 该装置可以包括通过接口耦合的源处理器和宿处理器。 宿处理器可以可操作以通过接口向源处理器发送同步信号。 源处理器可以根据同步信号来操作，以将数据发送到宿处理器。
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公开(公告)号：US09058676B2
公开(公告)日：2015-06-16
申请号：US13850565
申请日：2013-03-26
Applicant: Apple Inc.
Inventor： Brijesh Tripathi , Peter F. Holland , Albert C. Kuo
CPC classification number: G06T1/60 , G06F3/14 , G09G5/001 , G09G5/393 , G09G5/395 , G09G2330/02 , G09G2330/021 , G09G2340/02 , G09G2360/121
Abstract: In an embodiment, a display pipe is configured to composite one or more frames of images and/or video sequences to generate output frames for display. Additionally, the display pipe may be configured to compress an output frame and write the compressed frame to memory responsive to detecting static content in the output frames. The display pipe may also be configured to read the compressed frame from memory for display instead of reading the frames for compositing and display. In some embodiments, the display pipe may include an idle screen detect circuit configured to monitor the operation of the display pipe and/or the output frames to detect the static content.
Abstract translation: 在一个实施例中，显示管被配置为组合一个或多个图像帧和/或视频序列以产生用于显示的输出帧。 此外，显示管可以被配置为响应于检测输出帧中的静态内容而压缩输出帧并将压缩帧写入存储器。 显示管还可以被配置为从存储器读取压缩帧用于显示，而不是读取用于合成和显示的帧。 在一些实施例中，显示管道可以包括被配置为监视显示管道和/或输出框架的操作以检测静态内容的空闲屏幕检测电路。
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公开(公告)号：US20140292788A1
公开(公告)日：2014-10-02
申请号：US13850565
申请日：2013-03-26
Applicant: APPLE INC.
Inventor： Brijesh Tripathi , Peter F. Holland , Albert C. Kuo
IPC: G06T1/60
CPC classification number: G06T1/60 , G06F3/14 , G09G5/001 , G09G5/393 , G09G5/395 , G09G2330/02 , G09G2330/021 , G09G2340/02 , G09G2360/121
Abstract: In an embodiment, a display pipe is configured to composite one or more frames of images and/or video sequences to generate output frames for display. Additionally, the display pipe may be configured to compress an output frame and write the compressed frame to memory responsive to detecting static content in the output frames is detected. The display pipe may also be configured to read the compressed frame from memory for display instead of reading the frames for compositing and display. In some embodiments, the display pipe may include an idle screen detect circuit configured to monitor the operation of the display pipe and/or the output frames to detect the static content.
Abstract translation: 在一个实施例中，显示管被配置为组合一个或多个图像帧和/或视频序列以产生用于显示的输出帧。 此外，显示管可以被配置为压缩输出帧并且响应于检测到输出帧中的静态内容而将压缩帧写入存储器。 显示管还可以被配置为从存储器读取压缩帧用于显示，而不是读取用于合成和显示的帧。 在一些实施例中，显示管道可以包括被配置为监视显示管道和/或输出框架的操作以检测静态内容的空闲屏幕检测电路。
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公开(公告)号：US11024243B2
公开(公告)日：2021-06-01
申请号：US17034894
申请日：2020-09-28
Applicant: Apple Inc.
Inventor： Chaohao Wang , Brijesh Tripathi , Christopher Philip Alan Tann , David S. Zalatimo , Guy Cote , Hao Nan , Marc Albrecht , Paolo Sacchetto , Sandro H. Pintz
IPC: G09G3/36
Abstract: An electronic device may generate content that is to be displayed on a display. The display may have an array of liquid crystal display pixels for displaying image frames of the content. The image frames may be displayed with positive and negative polarities to help reduce charge accumulation effects. A charge accumulation tracker may analyze the image frames to determine when there is a risk of excess charge accumulation. The charge accumulation tracker may analyze information on gray levels, frame duration, and frame polarity. The charge accumulation tracker may compute a charge accumulation metric for entire image frames or may process subregions of each frame separately. When subregions are processed separately, each subregion may be individually monitored for a risk of excess charge accumulation.
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Patent Agency Ranking
公开(公告)号：US20210012733A1
公开(公告)日：2021-01-14
申请号：US17034894
申请日：2020-09-28
Applicant: Apple Inc.
Inventor： Chaohao Wang , Brijesh Tripathi , Christopher Philip Alan Tann , David S. Zalatimo , Guy Cote , Hao Nan , Marc Albrecht , Paolo Sacchetto , Sandro H. Pintz
IPC: G09G3/36
Abstract: An electronic device may generate content that is to be displayed on a display. The display may have an array of liquid crystal display pixels for displaying image frames of the content. The image frames may be displayed with positive and negative polarities to help reduce charge accumulation effects. A charge accumulation tracker may analyze the image frames to determine when there is a risk of excess charge accumulation. The charge accumulation tracker may analyze information on gray levels, frame duration, and frame polarity. The charge accumulation tracker may compute a charge accumulation metric for entire image frames or may process subregions of each frame separately. When subregions are processed separately, each subregion may be individually monitored for a risk of excess charge accumulation.
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公开(公告)号：US20180314355A1
公开(公告)日：2018-11-01
申请号：US16028377
申请日：2018-07-05
Applicant: Apple Inc.
Inventor： Brijesh Tripathi , Jean-Pierre S. Guillou
CPC classification number: G06F3/041 , G06T19/006 , G09G3/20 , G09G2320/029 , G09G2320/0606 , G09G2320/0613 , G09G2320/103 , G09G2330/02 , G09G2330/021 , G09G2340/0435 , G09G2354/00 , G09G2360/18
Abstract: An electronic device may be provided with a display. The display may be a variable frame rate display capable of adaptively adjusting a frame rate at which display frames are displayed in response to information associated with the current state of operation of the device. The information may be gathered using control circuitry in the electronic device. The control circuitry may gather the information for adjusting the frame rate by monitoring the electronic device power supply configuration, other device components, the type of content to be displayed, and user-input signals. The control circuitry may adjust the frame rate based on the gathered information by increasing or decreasing the frame rate. The control circuitry may be formed as a portion of display control circuitry for the device such as a display driver integrated circuit or may be formed as a portion of storage and processing circuitry external to the display.
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公开(公告)号：US20180166032A1
公开(公告)日：2018-06-14
申请号：US15890517
申请日：2018-02-07
Applicant: Apple Inc.
Inventor： Chaohao Wang , Brijesh Tripathi , Christopher Philip Alan Tann , David S. Zalatimo , Guy Cote , Hao Nan , Marc Albrecht , Paolo Sacchetto , Sandro H. Pintz
IPC: G09G3/36
CPC classification number: G09G3/3614 , G09G2320/0204 , G09G2320/0247 , G09G2320/0257 , G09G2320/046 , G09G2340/0435 , G09G2360/16
Abstract: An electronic device may generate content that is to be displayed on a display. The display may have an array of liquid crystal display pixels for displaying image frames of the content. The image frames may be displayed with positive and negative polarities to help reduce charge accumulation effects. A charge accumulation tracker may analyze the image frames to determine when there is a risk of excess charge accumulation. The charge accumulation tracker may analyze information on gray levels, frame duration, and frame polarity. The charge accumulation tracker may compute a charge accumulation metric for entire image frames or may process subregions of each frame separately. When subregions are processed separately, each subregion may be individually monitored for a risk of excess charge accumulation.
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公开(公告)号：US09785184B2
公开(公告)日：2017-10-10
申请号：US14833424
申请日：2015-08-24
Applicant: Apple Inc.
Inventor： Brijesh Tripathi
CPC classification number: G06F1/12 , G09G5/006 , G09G5/008 , G09G5/12 , G09G2330/021 , G09G2340/0435 , G09G2360/18 , G09G2370/047 , G09G2370/10
Abstract: Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The interface may include a primary link, an auxiliary link, and a hot plug detect link. The source processor may be operable to send a wake-up command to the sink processor via the auxiliary link. The source processor may send initialization parameters to the sink processor via the primary link. The initialization parameters may include a clock data recovery lock parameter and an idle parameter. Following the initialization parameters, the source processor may send a synchronization signal to the sink processor via the primary link. The source processor may then send a sleep command via the primary link to the sink processor.
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20.发明申请公开(公告)号：US20170177256A1
公开(公告)日：2017-06-22
申请号：US15447328
申请日：2017-03-02
Applicant: Apple Inc.
Inventor： Brijesh Tripathi , Shane J. Keil , Manu Gulati , Jung Wook Cho , Erik P. Machnicki , Gilbert H. Herbeck , Timothy J. Millet , Joshua P. de Cesare , Anand Dalal
CPC classification number: G06F12/0223 , G06F1/3206 , G06F1/3287 , G06F1/3293 , G06F3/0625 , G06F3/0632 , G06F3/0634 , G06F3/0673 , G06F9/4406 , G06F12/0646 , G06F13/1668 , G06F13/4068 , G06F13/4265 , G06F2212/1032 , G11C11/40615 , Y02D10/122 , Y02D10/151 , Y02D10/171 , Y02D50/20
Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.
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