公开(公告)号：US20230070053A1

公开(公告)日：2023-03-09

申请号：US17886102

申请日：2022-08-11

Applicant: Applied Materials, Inc.

Inventor： Han-Wen CHEN ,  Steven VERHAVERBEKE ,  Giback PARK

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/31

Abstract: The present disclosure relates to semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to semiconductor package devices having a stiffener framed formed thereon. The incorporation of the stiffener frame improves the structural integrity of the semiconductor package devices to mitigate warpage and/or collapse while simultaneously enabling utilization of thinner core substrates for improved signal integrity and power delivery between packaged devices.

公开(公告)号：US20220157740A1

公开(公告)日：2022-05-19

申请号：US17098597

申请日：2020-11-16

Applicant: Applied Materials, Inc.

Inventor： Steven VERHAVERBEKE ,  Han-Wen CHEN ,  Giback PARK ,  Chintan BUCH

IPC: H01L23/552 ,  H01L23/538 ,  H01L25/065 ,  H01L23/532

Abstract: The present disclosure relates to thin-form-factor semiconductor packages with integrated electromagnetic interference (“EMI”) shields and methods for forming the same. The packages described herein may be utilized to form high-density semiconductor devices. In certain embodiments, a silicon substrate is laser ablated to include one or more cavities and a plurality of vias surrounding the cavities. One or more semiconductor dies may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. A plurality of conductive interconnections are formed within the vias and may have contact points redistributed to desired surfaces of the die-embedded substrate assembly. Thereafter, an EMI shield is plated onto a surface of the die-embedded substrate assembly and connected to ground by at least one of the one or more conductive interconnections. The die-embedded substrate assembly may then be singulated and/or integrated with another semiconductor device.

公开(公告)号：US20210288027A1

公开(公告)日：2021-09-16

申请号：US16814785

申请日：2020-03-10

Applicant: Applied Materials, Inc.

Inventor： Kurtis LESCHKIES ,  Han-Wen CHEN ,  Steven VERHAVERBEKE ,  Giback PARK ,  Kyuil CHO ,  Jeffrey L. FRANKLIN ,  Wei-Sheng LEI

IPC: H01L25/065 ,  H05K1/14 ,  H01L25/00 ,  H01L23/495 ,  H01L23/522

Abstract: The present disclosure generally relates to stacked miniaturized electronic devices and methods of forming the same. More specifically, embodiments described herein relate to semiconductor device spacers and methods of forming the same. The semiconductor device spacers described herein may be utilized to form stacked semiconductor package assemblies, stacked PCB assemblies, and the like.

公开(公告)号：US20210234060A1

公开(公告)日：2021-07-29

申请号：US17227763

申请日：2021-04-12

Applicant: Applied Materials, Inc.

Inventor： Han-Wen CHEN ,  Steven VERHAVERBEKE ,  Giback PARK

IPC: H01L31/18

Abstract: The present disclosure relates to methods and apparatus for structuring a semiconductor substrate. In one embodiment, a method of substrate structuring includes applying a resist layer to a substrate optionally disposed on a carrier. The resist layer is patterned using ultraviolet radiation or laser ablation. The patterned portions of the resist layer are then transferred onto the substrate by micro-blasting to form desired features in the substrate while unexposed or un-ablated portions of the resist layer shield the rest of the substrate. The substrate is then exposed to an etch process and a de-bonding process to remove the resist layer and release the carrier.

公开(公告)号：US20180374718A1

公开(公告)日：2018-12-27

申请号：US15840900

申请日：2017-12-13

Applicant: Applied Materials, Inc.

Inventor： Han-Wen CHEN ,  Steven VERHAVERBEKE ,  Roman GOUK ,  Guan Huei SEE ,  Yu GU ,  Arvind SUNDARRAJAN ,  Kyuil CHO ,  Colin Costano NEIKIRK ,  Boyi FU

IPC: H01L21/56 ,  H01L23/31

Abstract: Embodiments of the present disclosure generally describe methods for minimizing the occurrence and the extent of die shift during the formation of a reconstituted substrate in fan-out wafer level packaging processes. Die shift is a process defect that occurs when a die (device) moves from its intended position within a reconstituted substrate during the formation thereof. Generally, the methods disclosed herein include depositing a device immobilization layer and/or a plurality of device immobilization beads over and/or adjacent to a plurality of singular devices (individual dies), and the carrier substrate they are positioned on, before forming a reconstituted substrate with an epoxy molding compound. The device immobilization layer and/or the plurality of device immobilization beads immobilize the plurality of singular devices and prevents them from shifting on the carrier substrate during the molding process.

公开(公告)号：US20170098555A1

公开(公告)日：2017-04-06

申请号：US15268158

申请日：2016-09-16

Applicant: Applied Materials, Inc.

Inventor： Roman GOUK ,  Han-Wen CHEN ,  Steven VERHAVERBEKE ,  Jean DELMAS

IPC: H01L21/67 ,  F26B21/14 ,  H01L21/677 ,  B08B7/00 ,  H01L21/02 ,  H01L21/687

CPC classification number: H01L21/67034 ,  B08B7/0021 ,  B08B7/0035 ,  C11D11/0047 ,  F26B21/14 ,  H01L21/02101 ,  H01L21/6704 ,  H01L21/67126 ,  H01L21/6719 ,  H01L21/67739 ,  H01L21/67748 ,  H01L21/68792

Abstract: Embodiments described herein generally relate to a processing chamber incorporating a small thermal mass which enable efficient temperature cycling for supercritical drying processes. The chamber generally includes a body, a liner, and an insulation element which enables the liner to exhibit a small thermal mass relative to the body. The chamber is also configured with suitable apparatus for generating and/or maintaining supercritical fluid within a processing volume of the chamber.

公开(公告)号：US20240222142A1

公开(公告)日：2024-07-04

申请号：US18089632

申请日：2022-12-28

Applicant: Applied Materials, Inc.

Inventor： Tapash CHAKRABORTY ,  Steven VERHAVERBEKE ,  Han-Wen CHEN ,  Kyuil CHO ,  Kent ZHAO ,  Gopi Chandran RAMACHANDRAN

IPC: H01L21/48 ,  H01L23/538 ,  H10B80/00

CPC classification number: H01L21/486 ,  H01L23/5384 ,  H01L23/5389 ,  H10B80/00

Abstract: Semiconductor packages and methods for metallization of non-conducting surfaces for fabricating semiconductor packages are provided. In an embodiment, the method includes depositing an adhesion layer on a polymeric surface by an electroless deposition process. The polymeric surface defines a sidewall of a through-hole via and the adhesion layer comprises a cobalt alloy or a nickel alloy. The method further includes depositing a copper seed layer on the adhesion layer by an immersion plating process. The copper seed layer displaces a portion of the adhesion layer. The method further includes filling the through-hole via with a copper containing layer.

公开(公告)号：US20240021533A1

公开(公告)日：2024-01-18

申请号：US18362433

申请日：2023-07-31

Applicant: Applied Materials, Inc.

Inventor： Han-Wen CHEN ,  Steven VERHAVERBEKE ,  Guan Huei SEE ,  Giback PARK ,  Giorgio CELLERE ,  Diego TONINI ,  Vincent DICAPRIO ,  Kyuil CHO

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/13 ,  H01L23/14 ,  H01L23/498 ,  H01L25/10 ,  H01L23/66 ,  H01Q1/22 ,  H01Q1/24 ,  H05K1/02 ,  H01L21/50 ,  H01L21/768 ,  H01L25/065 ,  H01L27/06

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/4864 ,  H01L23/13 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/49894 ,  H01L23/5384 ,  H01L23/5386 ,  H01L25/105 ,  H01L23/66 ,  H01Q1/2283 ,  H01Q1/243 ,  H05K1/0243 ,  H01L21/50 ,  H01L21/76802 ,  H01L23/5385 ,  H01L25/0657 ,  H01L27/0688 ,  H01L2225/1035 ,  H01L2225/107 ,  H01L2021/60007

Abstract: The present disclosure relates to thin-form-factor reconstituted substrates and methods for forming the same. The reconstituted substrates described herein may be utilized to fabricate homogeneous or heterogeneous high-density 3D integrated devices. In one embodiment, a silicon substrate is structured by direct laser patterning to include one or more cavities and one or more vias. One or more semiconductor dies of the same or different types may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. One or more conductive interconnections are formed in the vias and may have contact points redistributed to desired surfaces of the reconstituted substrate. The reconstituted substrate may thereafter be integrated into a stacked 3D device.

公开(公告)号：US20230148220A1

公开(公告)日：2023-05-11

申请号：US17973690

申请日：2022-10-26

Applicant: Applied Materials, Inc.

Inventor： Steven VERHAVERBEKE ,  Han-Wen CHEN

IPC: H01L23/498 ,  H10B80/00 ,  H01L23/00 ,  H01L21/48 ,  H01L23/538 ,  H01L23/367

CPC classification number: H01L23/49838 ,  H10B80/00 ,  H01L24/08 ,  H01L23/562 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49894 ,  H01L23/5385 ,  H01L23/49833 ,  H01L23/5386 ,  H01L23/3675 ,  H01L2224/08235 ,  H01L24/16 ,  H01L2224/16235 ,  H01L2924/1436 ,  H01L2924/3511

Abstract: The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor device package. In certain embodiments, a glass or silicon substrate is patterned by laser ablation to form structures for subsequent formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor device package, which may have one or more embedded double-sided dies therein. In certain embodiments, an insulating layer is formed over the substrate by laminating a pre-structured insulating film thereon. The insulating film may be pre-structured by laser ablation to form structures therein, followed by selective curing of sidewalls of the formed structures.

公开(公告)号：US20220028709A1

公开(公告)日：2022-01-27

申请号：US16938517

申请日：2020-07-24

Applicant: Applied Materials, Inc.

Inventor： Kurtis LESCHKIES ,  Jeffrey L. FRANKLIN ,  Wei-Sheng LEI ,  Steven VERHAVERBEKE ,  Jean DELMAS ,  Han-Wen CHEN ,  Giback PARK

IPC: H01L21/67 ,  H01L21/48 ,  B23K26/382 ,  B23K26/0622

Abstract: The present disclosure relates to systems and methods for fabricating semiconductor packages, and more particularly, for forming features in semiconductor packages by laser ablation. In one embodiment, the laser systems and methods described herein can be utilized to pattern a substrate to be utilized as a package frame for a semiconductor package having one or more interconnections formed therethrough and/or one or more semiconductor dies disposed therein. The laser systems described herein can produce tunable laser beams for forming features in a substrate or other package structure. Specifically, frequency, pulse width, pulse shape, and pulse energy of laser beams are tunable based on desired sizes of patterned features and on the material in which the patterned features are formed. The adjustability of the laser beams enables rapid and accurate formation of features in semiconductor substrates and packages with controlled depth and topography.