公开(公告)号：US20240071773A1

公开(公告)日：2024-02-29

申请号：US18232916

申请日：2023-08-11

Applicant: Applied Materials, Inc.

Inventor： Lei Liao ,  Yichuan Ling ,  Zhiyu Huang ,  Hideyuki Kanzawa ,  Fenglin Wang ,  Rajesh Prasad ,  Yung-Chen Lin ,  Chi-I Lang ,  Ho-yung David Hwang ,  Lequn Liu

IPC: H01L21/3115 ,  H01L21/02

CPC classification number: H01L21/31155 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02167

Abstract: Exemplary methods of semiconductor processing may include forming a layer of silicon-containing material on a semiconductor substrate. The methods may include performing a post-formation treatment on the layer of silicon-containing material to yield a treated layer of silicon-containing material. The methods may include contacting the treated layer of silicon-containing material with an adhesion agent. The methods may include forming a layer of a resist material on the treated layer of silicon-containing material.

公开(公告)号：US20230268188A1

公开(公告)日：2023-08-24

申请号：US17703254

申请日：2022-03-24

Applicant: Applied Materials, Inc.

Inventor： Sungho Jo ,  Rajesh Prasad ,  Kyuha Shim

IPC: H01L21/308 ,  H01L21/02 ,  H01L21/265

CPC classification number: H01L21/3086 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/26533 ,  H01L21/3081

Abstract: Methods of forming a silicon hardmask are disclosed. In one example, a method may include forming a silicon mask over a device layer, forming a carbon mask over the silicon mask, and forming an opening through the carbon mask. The method may further include forming an oxide layer within the opening by performing an ion implantation process to an upper surface of the silicon mask.

公开(公告)号：US11626284B2

公开(公告)日：2023-04-11

申请号：US17150781

申请日：2021-01-15

Applicant: Applied Materials, Inc.

Inventor： Keith T. Wong ,  Hurshvardhan Srivastava ,  Srinivas D. Nemani ,  Johannes M. van Meer ,  Rajesh Prasad

IPC: H01L21/02 ,  H01L29/66 ,  C23C14/58 ,  H01L29/76 ,  C23C16/30 ,  C23C16/455 ,  C23C16/56 ,  C23C14/48 ,  H01L29/24

Abstract: A method to form a 2-Dimensional transistor channel may include depositing an amorphous layer comprising a 2-dimensional material, implanting an implant species into the amorphous layer; and annealing the amorphous layer after the implanting. As such, the amorphous layer may form a doped crystalline layer.

公开(公告)号：US11551904B2

公开(公告)日：2023-01-10

申请号：US17015545

申请日：2020-09-09

Applicant: Applied Materials, Inc.

Inventor： Venkataramana R. Chavva ,  KyuHa Shim ,  Hans Gossmann ,  Edwin Arevalo ,  Scott Falk ,  Rajesh Prasad

IPC: H01J37/20 ,  H01L21/265 ,  H01J37/317 ,  H01L21/225 ,  H01J37/05 ,  H01J37/08

Abstract: A system and method that allows higher energy implants to be performed, wherein the peak concentration depth is shallower than would otherwise occur is disclosed. The system comprises an ion source, an accelerator, a platen and a platen orientation motor that allows large tilt angles. The system may be capable of performing implants of hydrogen ions at an implant energy of up to 5 MeV. By tilting the workpiece during an implant, the system can be used to perform implants that are typically performed at implant energies that are less than the minimum implant energy allowed by the system. Additionally, the resistivity profile of the workpiece after thermal treatment is similar to that achieved using a lower energy implant. In certain embodiments, the peak concentration depth may be reduced by 3 μm or more using larger tilt angles.

公开(公告)号：US20220367205A1

公开(公告)日：2022-11-17

申请号：US17318843

申请日：2021-05-12

Applicant: Applied Materials, Inc.

Inventor： Rajesh Prasad ,  Martin Seamons ,  Shan Tang ,  Qi Gao ,  Deven Raj Mittal ,  Kyuha Shim

IPC: H01L21/3115 ,  H01L21/02

Abstract: A method may include providing a substrate having, on a first surface of the substrate, a low dielectric constant layer characterized by a layer thickness. The method may include heating the substrate to a substrate temperature in a range of 200° C. to 550° C.; and directing an ion implant treatment to the low dielectric constant layer, while the substrate temperature is in the range of 200° C. to 550° C. As such, the ion implant treatment may include implanting a low weight ion species, at an ion energy generating an implant depth equal to 40% to 175% of the layer thickness.

公开(公告)号：US20240379376A1

公开(公告)日：2024-11-14

申请号：US18314481

申请日：2023-05-09

Applicant: Applied Materials, Inc.

Inventor： Rajesh Prasad ,  Yung-Chen Lin ,  Zhiyu Huang ,  Fenglin Wang ,  Chi-I Lang ,  Hoyung David Hwang ,  Edwin A. Arevalo ,  KyuHa Shim

IPC: H01L21/3115 ,  C23C14/48 ,  G03F7/004 ,  G03F7/09 ,  G03F7/11

Abstract: Disclosed herein are approaches for reducing EUV dose during formation of a patterned metal oxide photoresist. In one approach, a method may include providing a stack of layers atop a substrate, the stack of layers comprising a film layer, and implanting the film layer with ions. The method may further include depositing a metal oxide photoresist atop the film layer, and patterning the metal oxide photoresist.

公开(公告)号：US20230298892A1

公开(公告)日：2023-09-21

申请号：US18016926

申请日：2021-07-21

Applicant: Applied Materials, Inc.

Inventor： Rui Cheng ,  Rajesh Prasad ,  Karthik Janakiraman ,  Gautam K. Hemani ,  Krishna Nittala ,  Shan Tang ,  Qi Gao

IPC: H01L21/265 ,  H01L21/02

CPC classification number: H01L21/26506 ,  H01L21/02532 ,  H01L21/02592

Abstract: Exemplary methods of semiconductor processing may include forming a layer of amorphous silicon on a semiconductor substrate. The layer of amorphous silicon may be characterized by a first amount of hydrogen incorporation. The methods may include performing a beamline ion implantation process or plasma doping process on the layer of amorphous silicon. The methods may include removing hydrogen from the layer of amorphous silicon to a second amount of hydrogen incorporation less than the first amount of hydrogen incorporation.

公开(公告)号：US20220108886A1

公开(公告)日：2022-04-07

申请号：US17150781

申请日：2021-01-15

Applicant: Applied Materials, Inc.

Inventor： Keith T. Wong ,  Hurshvardhan Srivastava ,  Srinivas D. Nemani ,  Johannes M. van Meer ,  Rajesh Prasad

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/24 ,  H01L29/76 ,  C23C16/30 ,  C23C16/455 ,  C23C16/56 ,  C23C14/48 ,  C23C14/58

Abstract: A method to form a 2-Dimensional transistor channel may include depositing an amorphous layer comprising a 2-dimensional material, implanting an implant species into the amorphous layer; and annealing the amorphous layer after the implanting. As such, the amorphous layer may form a doped crystalline layer.

公开(公告)号：US11114299B2

公开(公告)日：2021-09-07

申请号：US16569944

申请日：2019-09-13

Applicant: APPLIED Materials, Inc.

Inventor： Qintao Zhang ,  Kyu-Ha Shim ,  Rajesh Prasad

IPC: H01L21/027 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/768 ,  H01L29/66 ,  H01L21/033

Abstract: A method of forming surface features in a hardmask layer, including etching a first surface feature into the hardmask layer, the first surface feature having a first critical dimension, performing an ion implantation process on the first surface feature to make the first surface feature resistant to subsequent etching processes, etching a second surface feature into the hardmask layer adjacent the first surface feature, wherein the first critical dimension is preserved.

公开(公告)号：US20210005445A1

公开(公告)日：2021-01-07

申请号：US16569944

申请日：2019-09-13

Applicant: APPLIED Materials, Inc.

Inventor： Qintao Zhang ,  Kyu-Ha Shim ,  Rajesh Prasad

IPC: H01L21/027 ,  H01L29/66 ,  H01L21/3115 ,  H01L21/311 ,  H01L21/768 ,  H01L21/3105

Abstract: A method of forming surface features in a hardmask layer, including etching a first surface feature into the hardmask layer, the first surface feature having a first critical dimension, performing an ion implantation process on the first surface feature to make the first surface feature resistant to subsequent etching processes, etching a second surface feature into the hardmask layer adjacent the first surface feature, wherein the first critical dimension is preserved.