公开(公告)号：US20140205818A1

公开(公告)日：2014-07-24

申请号：US14005964

申请日：2012-03-19

Applicant: Evan L. Schwartz ,  Wei Min Chan ,  Jin-Kyun Lee ,  Sandip Tiwari ,  Christopher K. Ober

Inventor： Evan L. Schwartz ,  Wei Min Chan ,  Jin-Kyun Lee ,  Sandip Tiwari ,  Christopher K. Ober

IPC: G03F7/16 ,  H01L21/027

CPC classification number: G03F7/16 ,  B81C1/00031 ,  B81C2201/0149 ,  G03F7/0002 ,  G03F7/038 ,  H01L21/027 ,  Y10T428/24851

Abstract: A method for forming patterns of organic polymer materials. The method can be used to form a layer with two patterned organic polymer materials. The photoresist and solvents used in the photoresist deposition and removal steps do not substantially affect the organic polymer materials.

Abstract translation: 一种形成有机聚合物材料图案的方法。 该方法可用于形成具有两个图案化有机聚合物材料的层。 在光致抗蚀剂沉积和去除步骤中使用的光致抗蚀剂和溶剂基本上不影响有机聚合物材料。

公开(公告)号：US20060013876A1

公开(公告)日：2006-01-19

申请号：US10518909

申请日：2003-06-25

Applicant: Braj Lohray ,  Sandip Tiwari ,  Raveendra Pai ,  Krishna Murthy ,  Pavak Mehta

Inventor： Braj Lohray ,  Sandip Tiwari ,  Raveendra Pai ,  Krishna Murthy ,  Pavak Mehta

IPC: A61K9/24

CPC classification number: A61K9/0065

Abstract: Present invention relates to a novel pharmaceutical composition containing an active ingredient(s) which is retained in the stomach or upper part of gastrointestinal tract for controlled delivery of medicament for improved local treatment, and/or better absorption from upper parts of gastrointestinal tract for effective therapeutic results. Present invention also provides a method for preparation of the said dosage form preferably in the form of a bilayer tablet, in which one layer constitutes for spatial control and the other being for temporal control.

Abstract translation: 本发明涉及含有活性成分的新型药物组合物，其保留在胃或胃肠道上部，用于控制递送用于改善局部治疗的药物和/或从胃肠道上部更好地吸收以有效地 治疗结果。 本发明还提供了优选以双层片剂形式制备所述剂型的方法，其中一层构成用于空间控制，另一层构成用于时间控制。

公开(公告)号：US06177289B1

公开(公告)日：2001-01-23

申请号：US09205433

申请日：1998-12-04

Applicant: John Crow ,  Steve Koester ,  Daniel M. Kuchta ,  Dennis L. Rogers ,  Devendra Sadana ,  Sandip Tiwari

Inventor： John Crow ,  Steve Koester ,  Daniel M. Kuchta ,  Dennis L. Rogers ,  Devendra Sadana ,  Sandip Tiwari

IPC: H01L2166

CPC classification number: H01L31/03529 ,  H01L31/035281 ,  H01L31/105 ,  Y02E10/50

Abstract: A monolithic semiconductor optical detector is formed on a substrate having a plurality of substantially parallel trenches etched therein. The trenches are further formed as a plurality of alternating N-type and P-type trench regions separated by pillar regions of the substrate which operate as an I region between the N and P trench regions. First and second contacts are formed on the surface of the substrate and interconnect the N-type trench regions and the P-type trench regions, respectively. Preferably, the trenches are etched with a depth comparable to an optical extinction length of optical radiation to which the detector is responsive.

Abstract translation: 单片半导体光检测器形成在其上蚀刻有多个基本上平行的沟槽的衬底上。 沟槽还形成为由作为N沟道区域和P沟道区域之间的I区域的基板的柱状区域分离的多个交替的N型和P型沟槽区域。 第一和第二触点形成在衬底的表面上并分别互连N型沟槽区和P型沟槽区。 优选地，以与检测器响应的光辐射的光消光长度相当的深度蚀刻沟槽。

公开(公告)号：US6057212A

公开(公告)日：2000-05-02

申请号：US72294

申请日：1998-05-04

Applicant: Kevin Kok Chan ,  Christopher Peter D'Emic ,  Erin Catherine Jones ,  Paul Michael Solomon ,  Sandip Tiwari

Inventor： Kevin Kok Chan ,  Christopher Peter D'Emic ,  Erin Catherine Jones ,  Paul Michael Solomon ,  Sandip Tiwari

IPC: H01L21/762 ,  H01L21/30 ,  H01L21/46

CPC classification number: H01L21/76251

Abstract: A method of forming a semiconductor structure, includes steps of growing an oxide layer on a substrate to form a first wafer, separately forming a metal film on an oxidized substrate to form a second wafer, attaching the first and second wafers, performing a heat cycle for the first and second wafers to form a bond between the first and second wafers, and detaching a portion of the first wafer from the second wafer. Thus, a device, such as a back-plane for a semiconductor device, formed by the method includes an oxidized substrate, a metal film formed on the oxidized substrate forming a back-gate, a back-gate oxide formed on the back-gate, and a silicon layer formed on the back-gate oxide.

Abstract translation: 一种形成半导体结构的方法包括以下步骤：在衬底上生长氧化物层以形成第一晶片，在氧化衬底上单独形成金属膜以形成第二晶片，附接第一和第二晶片，执行热循环 用于第一和第二晶片在第一和第二晶片之间形成结合，并且将第一晶片的一部分与第二晶片分离。 因此，通过该方法形成的半导体装置的背面等装置包括氧化基板，形成在背栅的氧化基板上形成的金属膜，形成在背栅上的背栅氧化物 ，以及形成在背栅氧化层上的硅层。

公开(公告)号：US5920086A

公开(公告)日：1999-07-06

申请号：US972980

申请日：1997-11-19

Applicant: Roger Morton MacFarlane ,  James Anthony Misewich ,  Sanjay Sethi ,  Sandip Tiwari

Inventor： Roger Morton MacFarlane ,  James Anthony Misewich ,  Sanjay Sethi ,  Sandip Tiwari

IPC: H01L33/26 ,  H05B33/14 ,  H01L33/00

CPC classification number: H01L33/26

Abstract: A device for generating radiant energy comprising a first electrode, a second electrode spaced apart from said first electrode, a material disposed between and in electrical communication with first and second electrodes, which emits radiant energy upon activation. This material is a rare earth metal oxide or a rare earth metal halide.

Abstract translation: 一种用于产生辐射能的装置，包括第一电极，与所述第一电极间隔开的第二电极，设置在第一和第二电极之间并与之电连通的材料，其在激活时发射辐射能。 该材料是稀土金属氧化物或稀土金属卤化物。

公开(公告)号：US5508543A

公开(公告)日：1996-04-16

申请号：US236751

申请日：1994-04-29

Applicant: Allan M. Hartstein ,  Michael A. Tischler ,  Sandip Tiwari

Inventor： Allan M. Hartstein ,  Michael A. Tischler ,  Sandip Tiwari

IPC: H01L21/8247 ,  H01L29/49 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76

CPC classification number: H01L29/4975 ,  H01L29/49 ,  H01L29/4916 ,  H01L29/4966 ,  H01L29/7883

Abstract: A floating gate is inserted into the gate stack of an EEPROM cell. For an N channel EEPROM device, the floating gate is composed of a material having a conduction band edge (or fermi energy in the case of a metal or composite that includes a metal) at least one and preferably several kT electron volts below the conduction band edge of the channel region. The floating gate material thus has a larger electron affinity than the material of the channel region. This allows the insulator separating the floating gate and the channel to be made suitable thin (less than 100 angstroms) to reduce the writing voltage and to increase the number of write cycles that can be done without failure, without having charge stored on the floating gate tunnel back out to the channel region during read operations. For a P channel EEPROM device, the floating gate is composed of a material having a valence band edge (or fermi energy in the case of a metal or a composite that includes a metal) at least one and preferably several kT (eV) above the valence band edge of the channel region.

Abstract translation: 浮动栅极插入EEPROM单元的栅极堆叠中。 对于N沟道EEPROM器件，浮置栅极由具有导带边缘的材料（或在包含金属的金属或复合材料的情况下的费米能量）组成，其至少一个且优选地在导带之下几个kT电子伏特 通道区域的边缘。 浮栅材料因此具有比沟道区的材料更大的电子亲和力。 这允许将浮动栅极和沟道分离成绝缘体（小于100埃）以减小写入电压并增加可以在没有故障的情况下完成的写入周期数，而不会在浮置栅极上存储电荷 在读取操作期间隧道返回到通道区域。 对于P沟道EEPROM器件，浮动栅极由具有价带边缘（或金属或包含金属的复合材料的情况下的费米能量）的材料组成，至少一个且优选地几个kT（eV） 通道区域的价带边缘。

公开(公告)号：US4987095A

公开(公告)日：1991-01-22

申请号：US207700

申请日：1988-06-15

Applicant: John Batey ,  Sandip Tiwari ,  Steven L. Wright

Inventor： John Batey ,  Sandip Tiwari ,  Steven L. Wright

IPC: H01L29/78 ,  H01L21/203 ,  H01L21/205 ,  H01L21/28 ,  H01L21/31 ,  H01L21/314 ,  H01L21/336 ,  H01L29/267 ,  H01L29/43

CPC classification number: H01L29/66522 ,  H01L21/28264 ,  H01L21/314 ,  H01L29/267 ,  H01L29/432 ,  Y10S148/149 ,  Y10S438/933 ,  Y10S438/958

Abstract: Unpinned epitaxial metal-oxide-compound semiconductor structures are disclosed and a method of fabricating such structures is described. Epitaxial layers of compound semiconductor are grown by MBE which result in the formation of a smooth surface having a stabilized reconstruction. An elemental semiconductor layer is deposited epitaxially in-situ with the compound semiconductor layer which unpins the surface Fermi level. A layer of insulator material is then deposited on the elemental semiconductor layer by PECVD. In one embodiment, the compound semiconductor is GaAs and the elemental semiconductor is Si. The insulator material is a layer of high quality SiO.sub.2. A metal gate is deposited on the SiO.sub.2 layer to form an MOS device. The epitaxial GaAs layer has a density of states which permits the interface Fermi level to be moved through the entire forbidden energy gap. In another embodiment, the SiO.sub.2 deposition completely consumes the interface Si layer so that the resulting MOS device comprises SiO.sub.2 directly overlying the GaAs layer.

公开(公告)号：US4849802A

公开(公告)日：1989-07-18

申请号：US233851

申请日：1988-08-16

Applicant: Thomas N. Jackson ,  Masanori Murakami ,  William H. Price ,  Sandip Tiwari ,  Jerry M. Woodall ,  Steven L. Wright

Inventor： Thomas N. Jackson ,  Masanori Murakami ,  William H. Price ,  Sandip Tiwari ,  Jerry M. Woodall ,  Steven L. Wright

IPC: H01L29/45

CPC classification number: H01L29/452

Abstract: In a semiconductor device, a contact with low resistance to a III-V compound semiconductor substrate was fabricated using refractory materials and small amounts of indium as the contact material. The contact material was formed by depositing Mo, Ge and W with small amounts of In onto doped GaAs wafers. The contact resistance less than 1.0 ohm millimeter was obtained after annealing at 800.degree. C. and the resistance did not increase after subsequent prolonged annealing at 400.degree. C.

Abstract translation: 在半导体器件中，使用耐火材料和少量的铟作为接触材料制造具有低耐III-V化合物半导体衬底的接触。 通过将Mo，Ge和W与少量的In沉积到掺杂的GaAs晶片上形成接触材料。 800℃退火后获得小于1.0欧姆毫米的接触电阻，在400℃下经过长时间的退火后，电阻不增加。

公开(公告)号：US08987701B2

公开(公告)日：2015-03-24

申请号：US13322379

申请日：2010-05-28

Applicant: Sandip Tiwari ,  Ravishankar Sundararaman ,  Sang Hyeon Lee ,  Moonkyung Kim

Inventor： Sandip Tiwari ,  Ravishankar Sundararaman ,  Sang Hyeon Lee ,  Moonkyung Kim

IPC: H01L47/00 ,  H01L29/68 ,  H01L29/51

CPC classification number: H01L29/685 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517

Abstract: In one embodiment there is set forth a method comprising providing a semiconductor structure having an electrode, wherein the providing includes providing a phase transition material region and wherein the method further includes imparting energy to the phase transition material region to induce a phase transition of the phase transition material region. By inducing a phase transition of the phase transition material region, a state of the semiconductor structure can be changed. There is further set forth an apparatus comprising a structure including an electrode and a phase transition material region, wherein the apparatus is operative for imparting energy to the phase transition material region to induce a phase transition of the phase transition material region without the phase transition of the phase transition material region being dependent on electron transport through the phase transition material region.

Abstract translation: 在一个实施例中，提出了一种方法，包括提供具有电极的半导体结构，其中所述提供包括提供相变材料区域，并且其中所述方法还包括赋予相变材料区域能量以引起相位的相变 过渡材料区域。 通过引起相变材料区域的相变，可以改变半导体结构的状态。 还提出了一种装置，其包括包括电极和相变材料区域的结构，其中该装置可操作以将能量传递给相变材料区域，以引起相变材料区域的相变而不发生相变 相变材料区域依赖于通过相变材料区域的电子传输。

公开(公告)号：US08553455B2

公开(公告)日：2013-10-08

申请号：US11528712

申请日：2006-09-27

Applicant: Sandip Tiwari ,  Chung Woo Kim

Inventor： Sandip Tiwari ,  Chung Woo Kim

IPC: G11C11/34

CPC classification number: H01L27/115 ,  B81B3/0072 ,  B81B2201/016 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/0016 ,  G11C13/025 ,  G11C23/00 ,  G11C2213/14 ,  G11C2213/17 ,  G11C2213/77 ,  H01H9/547 ,  H01H59/0009 ,  H01H61/0107 ,  H01L21/28273 ,  H01L27/112 ,  H01L29/66825 ,  H01L29/785

Abstract: Mechanical devices having bistable positions are utilized to form switches and memory devices. The devices are actuatable to different positions and may be coupled to a transistor device in various configurations to provide memory devices. Actuation mechanisms include electrostatic methods and heat. In one form, the mechanical device forms a gate for a field effect transistor. In a further form, the device may be a switch that may be coupled to the transistor in various manners to affect its electrical characteristics when on and off. The memory switch in one embodiment comprises side walls formed with tensile or compressive films. A cross point switch is formed from a plurality of intersecting conductive rows and columns of conductors. Actuatable switches are positioned between each intersection of the rows and columns such that each intersection is independently addressable.

Abstract translation: 利用具有双稳态位置的机械装置来形成开关和存储装置。 这些器件可被驱动到不同的位置，并且可以以各种配置耦合到晶体管器件以提供存储器件。 致动机制包括静电法和热量。 在一种形式中，机械装置形成用于场效应晶体管的栅极。 在另一种形式中，器件可以是开关，其可以以各种方式耦合到晶体管，以便在接通和断开时影响其电特性。 在一个实施例中的存储器开关包括由拉伸或压缩膜形成的侧壁。 交叉点开关由多个交叉的导电行和导体列形成。 可执行开关位于行和列的每个交叉点之间，使得每个交叉点可独立寻址。