公开(公告)号：US09354611B2

公开(公告)日：2016-05-31

申请号：US14526773

申请日：2014-10-29

Applicant: Atmel Corporation

Inventor： Frode Milch Pedersen ,  Laurentiu Birsan ,  Frederic Igier

IPC: H03M1/50 ,  G04F10/00 ,  H03M1/12

CPC classification number: H03M1/1215

Abstract: In some implementations, a method comprises: generating, by an event system of an integrated circuit, a first event signal in response to a clock signal; distributing the first event signal to a first digital converter, where the first event signal triggers conversion of a first analog signal to a first digital value by the first digital converter; generating, by the event system, a second event signal in response to the clock signal; and distributing the second event signal to a second digital converter, where the second event signal triggers conversion of a second analog signal to a second digital value.

Abstract translation: 在一些实现中，一种方法包括：响应于时钟信号，由集成电路的事件系统产生第一事件信号; 将第一事件信号分配给第一数字转换器，其中第一事件信号通过第一数字转换器触发第一模拟信号转换为第一数字值; 由所述事件系统响应于所述时钟信号产生第二事件信号; 以及将所述第二事件信号分配给第二数字转换器，其中所述第二事件信号触发第二模拟信号的转换为第二数字值。

公开(公告)号：US20160124393A1

公开(公告)日：2016-05-05

申请号：US14526773

申请日：2014-10-29

Applicant: Atmel Corporation

Inventor： Frode Milch Pedersen ,  Laurentiu Birsan ,  Frederic Igier

IPC: G04F10/00 ,  H03M1/12

CPC classification number: H03M1/1215

Abstract: In some implementations, a method comprises: generating, by an event system of an integrated circuit, a first event signal in response to a clock signal; distributing the first event signal to a first digital converter, where the first event signal triggers conversion of a first analog signal to a first digital value by the first digital converter; generating, by the event system, a second event signal in response to the clock signal; and distributing the second event signal to a second digital converter, where the second event signal triggers conversion of a second analog signal to a second digital value.

Abstract translation: 在一些实现中，一种方法包括：响应于时钟信号，由集成电路的事件系统产生第一事件信号; 将第一事件信号分配给第一数字转换器，其中第一事件信号通过第一数字转换器触发第一模拟信号转换为第一数字值; 由所述事件系统响应于所述时钟信号产生第二事件信号; 以及将所述第二事件信号分配给第二数字转换器，其中所述第二事件信号触发第二模拟信号的转换为第二数字值。

公开(公告)号：US20160048197A1

公开(公告)日：2016-02-18

申请号：US14462367

申请日：2014-08-18

Applicant: Atmel Corporation

Inventor： Ingar Hanssen ,  Frode Milch Pedersen

IPC: G06F1/32 ,  G01R21/00

CPC classification number: G06F1/3293 ,  G01R22/10 ,  H02M3/07 ,  H02M3/156 ,  H02M2001/0009 ,  H02M2001/0012

Abstract: A circuit includes a pulse generator coupled to a switch mode power supply. The switch mode power supply includes a switching component configured for transferring a charge to an energy storage component in response to pulses provided by the pulse generator. A pulse counter is coupled to the pulse generator or the switching component and configured to count pulses over a time period and thereby generate a pulse count. A converter coupled to the pulse counter is configured to generate a power measurement for the time period based on the pulse count. If the switch mode power supply has different modes of operation, a different counter may be used for each mode.

Abstract translation: 电路包括耦合到开关模式电源的脉冲发生器。 开关模式电源包括被配置为响应于由脉冲发生器提供的脉冲将电荷传送到能量存储部件的开关部件。 脉冲计数器耦合到脉冲发生器或开关部件，并且被配置为在一段时间内对脉冲进行计数，从而产生脉冲计数。 耦合到脉冲计数器的A转换器被配置为基于脉冲计数来产生该时间段的功率测量。 如果开关模式电源具有不同的工作模式，则可以对每个模式使用不同的计数器。

公开(公告)号：US20140281156A1

公开(公告)日：2014-09-18

申请号：US13941671

申请日：2013-07-15

Applicant: ATMEL CORPORATION

Inventor： Frode Milch Pedersen ,  Sebastien Jouin ,  Ian Fullerton

IPC: G06F12/02

CPC classification number: G06F3/0611 ,  G06F3/0655 ,  G06F3/0679 ,  G06F13/1689 ,  G06F13/4217 ,  G06F13/4243 ,  Y02D10/14 ,  Y02D10/151

Abstract: A latch signal is received from a non-volatile memory device that is indicative of a current access time for the non-volatile memory device. The access time represents an amount of time required for the non-volatile memory device to make data available responsive to a request for data. A bus system clock signal is received. The latch signal is evaluated and a wait state for the non-volatile memory device is adjusted based on the evaluation. The wait state represents a number of cycles of the bus system clock used by a central processing unit for an access of the non-volatile memory device. A bus system data ready signal that is triggered based on the adjusted wait state is produced. The bus system data ready signal, when triggered, indicates that data is available responsive to the request.

Abstract translation: 从非易失性存储器件接收指示非易失性存储器件的当前访问时间的锁存信号。 访问时间表示非易失性存储器件根据数据请求使数据可用的时间量。 接收总线系统时钟信号。 评估锁存信号，并且基于评估来调整非易失性存储器件的等待状态。 等待状态表示由中央处理单元用于访问非易失性存储器件的总线系统时钟的周期数。 产生基于调整后的等待状态触发的总线系统数据就绪信号。 当触发时，总线系统数据就绪信号表示响应于该请求可用数据。

公开(公告)号：US20180046582A1

公开(公告)日：2018-02-15

申请号：US15294413

申请日：2016-10-14

Applicant: Atmel Corporation

Inventor： Frode Milch Pedersen ,  Sylvain Garnier ,  Ian Fullerton ,  Xavier Leprevost

IPC: G06F12/1009 ,  G06F3/06 ,  G06F12/02

CPC classification number: G06F12/1009 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/2022 ,  G06F2212/7201

Abstract: In an embodiment, a method comprises: obtaining a virtual bus address; translating the virtual bus address to a physical address of a portion of NVM storing first data; determining that the first portion of NVM has been allocated previously; reading the first data from the first portion of NVM; determining whether writing second data to the first portion of the NVM would change one or more bits in the first data; responsive to the determining that a write operation only changes data bits in the first data from 1 to 0, writing the second data over the first data stored in the first portion of NVM; and responsive to the determining that one or more bits in the first data would be flipped from 0 to 1, reallocating the first portion of NVM to a second portion of NVM, copying the first data from the first portion of NVM to the second portion of NVM with the first data modified by the second data.

公开(公告)号：US20180011804A1

公开(公告)日：2018-01-11

申请号：US15277971

申请日：2016-09-27

Applicant: Atmel Corporation

Inventor： Frode Milch Pedersen

IPC: G06F13/16 ,  G06F13/24

Abstract: The disclosed embodiments provide a mechanism to support implementation of semaphores or messaging signals between masters in a multi-master system, or between tasks in a single master system. A semaphore flag register contains one or more bits indicating whether resources are free or busy. The register is aliased to allow atomic read-and-clear of individual bits in the register. Masters poll the status of a resource until the resource reads as free. Alternatively, interrupts or events per master can be implemented to indicate availability of a resource.

公开(公告)号：US09823734B2

公开(公告)日：2017-11-21

申请号：US14462367

申请日：2014-08-18

Applicant: Atmel Corporation

Inventor： Ingar Hanssen ,  Frode Milch Pedersen

IPC: G05F1/00 ,  G06F1/32 ,  G01R22/10 ,  H02M3/07 ,  H02M3/156 ,  H02M1/00

CPC classification number: G06F1/3293 ,  G01R22/10 ,  H02M3/07 ,  H02M3/156 ,  H02M2001/0009 ,  H02M2001/0012

Abstract: A circuit includes a pulse generator coupled to a switch mode power supply. The switch mode power supply includes a switching component configured for transferring a charge to an energy storage component in response to pulses provided by the pulse generator. A pulse counter is coupled to the pulse generator or the switching component and configured to count pulses over a time period and thereby generate a pulse count. A converter coupled to the pulse counter is configured to generate a power measurement for the time period based on the pulse count. If the switch mode power supply has different modes of operation, a different counter may be used for each mode.

公开(公告)号：US20160321472A1

公开(公告)日：2016-11-03

申请号：US14698330

申请日：2015-04-28

Applicant: Atmel Corporation

Inventor： Frode Milch Pedersen

IPC: G06F21/85 ,  G06F21/74

CPC classification number: G06F21/85 ,  G06F21/575 ,  G06F21/74

Abstract: Systems, methods and computer-readable mediums are disclosed for providing secure access in a microcontroller system. In some implementations, a microcontroller system comprises a system bus and a secure central processing unit (CPU) coupled to the system bus. The secure CPU is configured to provide secure access to the system bus. A non-secure CPU is also coupled to the system bus and is configured to provide non-secure access to the system bus. A non-secure memory is coupled to the system bus and is configured to allow the secure CPU and the non-secure CPU to exchange data and communicate with each other. A peripheral access controller (PAC) is coupled to the system bus and configured to enable secure access to a peripheral by the secure CPU while disabling non-secure access to the peripheral based upon a non-secure state of the non-secure CPU.

Abstract translation: 公开了用于在微控制器系统中提供安全访问的系统，方法和计算机可读介质。 在一些实现中，微控制器系统包括系统总线和耦合到系统总线的安全中央处理单元（CPU）。 安全CPU被配置为提供对系统总线的安全访问。 非安全CPU还耦合到系统总线，并且被配置为提供对系统总线的非安全访问。 非安全存储器耦合到系统总线，并且被配置为允许安全CPU和非安全CPU交换数据并彼此通信。 外围设备访问控制器（PAC）被耦合到系统总线，并且被配置为使安全CPU能够安全地访问外围设备，同时基于非安全CPU的非安全状态禁止对外围设备的非安全访问。

公开(公告)号：US09442873B2

公开(公告)日：2016-09-13

申请号：US14510529

申请日：2014-10-09

Applicant: Atmel Corporation

Inventor： Laurentiu Birsan ,  Frode Milch Pedersen ,  Nicolas Graffet ,  Stein Danielsen ,  Sebastien Jouin

IPC: G06F13/28 ,  G01R31/08

CPC classification number: G06F13/28

Abstract: Systems and methods for direct memory access are described. One example system includes a memory module that includes a first memory portion that maintains transfer descriptors of direct memory access (DMA) channels, and a second memory portion that maintains transfer descriptors of enabled DMA channels. The system includes a controller coupled to the memory module, the controller includes one or more DMA channels coupled to a system bus, a channel arbiter that selects one of the enabled DMA channels as an active DMA channel for data transfer including re-arbitrating after each burst or beat in a given transfer, and an active channel buffer that receives a transfer descriptor of the active DMA channel from the second memory portion. The controller is configured to write back the transfer descriptor of the active DMA channel into the second memory portion when the active DMA channel loses arbitration.

Abstract translation: 描述用于直接存储器访问的系统和方法。 一个示例系统包括存储器模块，该存储器模块包括保持直接存储器访问（DMA）通道的传送描述符的第一存储器部分和维持已使能的DMA通道的传送描述符的第二存储器部分。 该系统包括耦合到存储器模块的控制器，控制器包括耦合到系统总线的一个或多个DMA通道，通道仲裁器，其选择使能的DMA通道中的一个作为用于数据传输的活动DMA通道，包括在每一个之后重新仲裁 在给定传送中突发或跳动，以及从第二存储器部分接收活动DMA通道的传输描述符的活动通道缓冲器。 控制器被配置为当活动DMA通道失去仲裁时将有效DMA通道的传输描述符写回第二存储器部分。

公开(公告)号：US08880756B1

公开(公告)日：2014-11-04

申请号：US13932925

申请日：2013-07-01

Applicant: Atmel Corporation

Inventor： Laurentiu Birsan ,  Frode Milch Pedersen ,  Nicolas Graffet ,  Stein Danielsen ,  Sebastien Jouin

IPC: G06F13/28 ,  G01R31/08

CPC classification number: G06F13/28

Abstract: Systems and methods for direct memory access are described. One example system includes a memory module that includes a first memory portion that maintains transfer descriptors of direct memory access (DMA) channels, and a second memory portion that maintains transfer descriptors of enabled DMA channels. The system includes a controller coupled to the memory module, the controller includes one or more DMA channels coupled to a system bus, a channel arbiter that selects one of the enabled DMA channels as an active DMA channel for data transfer including re-arbitrating after each burst or beat in a given transfer, and an active channel buffer that receives a transfer descriptor of the active DMA channel from the second memory portion. The controller is configured to write back the transfer descriptor of the active DMA channel into the second memory portion when the active DMA channel loses arbitration.

Abstract translation: 描述用于直接存储器访问的系统和方法。 一个示例系统包括存储器模块，该存储器模块包括保持直接存储器访问（DMA）通道的传送描述符的第一存储器部分和维持已使能的DMA通道的传送描述符的第二存储器部分。 该系统包括耦合到存储器模块的控制器，控制器包括耦合到系统总线的一个或多个DMA通道，通道仲裁器，其选择使能的DMA通道中的一个作为用于数据传输的活动DMA通道，包括在每一个之后重新仲裁 在给定传送中突发或跳动，以及从第二存储器部分接收活动DMA通道的传输描述符的活动通道缓冲器。 控制器被配置为当活动DMA通道失去仲裁时将有效DMA通道的传输描述符写回第二存储器部分。