公开(公告)号：US09612983B2

公开(公告)日：2017-04-04

申请号：US13964971

申请日：2013-08-12

Applicant: Atmel Corporation

Inventor： Frode Milch Pedersen ,  Sebastien Jouin ,  Stein Danielsen ,  Thierry Delalande ,  Ivar Holand ,  Mona Opsahl

IPC: G06F13/14 ,  G06F13/362 ,  G06F13/10

CPC classification number: G06F13/362 ,  G06F13/102 ,  G06F13/14

Abstract: A flexible-width peripheral register mapping is disclosed for accessing peripheral registers on a peripheral bus.

公开(公告)号：US09552385B2

公开(公告)日：2017-01-24

申请号：US13965020

申请日：2013-08-12

Applicant: Atmel Corporation

Inventor： Frode Milch Pedersen ,  Sebastien Jouin ,  Stein Danielsen ,  Francois Fosse ,  Thierry Delalande ,  Ivar Holand ,  James Hallman

IPC: G06F13/362 ,  G06F17/30 ,  G06F13/40 ,  G06F13/12 ,  G06F11/00

CPC classification number: G06F9/526 ,  G06F11/00 ,  G06F11/004 ,  G06F13/122 ,  G06F13/28 ,  G06F13/362 ,  G06F13/4004 ,  G06F13/4282 ,  G06F17/30362 ,  G06F2201/825

Abstract: Implementations are disclosed for a centralized peripheral access controller (PAC) that is configured to protect one or more peripheral components in a system. In some implementations, the PAC stores data that can be set or cleared by software. The data corresponds to an output signal of the PAC that is routed to a corresponding peripheral component. When the data indicates that the peripheral is “unlocked” the PAC will allow write transfers to registers in the peripheral component. When the data indicates that the peripheral component is “locked” the PAC will refuse write transfers to registers in the peripheral component and terminate with an error.

Abstract translation: 公开了针对被配置为保护系统中的一个或多个外围组件的中央外围设备访问控制器（PAC）的实现。 在一些实现中，PAC存储可以由软件设置或清除的数据。 该数据对应于被路由到对应的外围组件的PAC的输出信号。 当数据指示外设“未锁定”时，PAC将允许写入传输到外设组件中的寄存器。 当数据指示外设组件“锁定”时，PAC将拒绝对外设组件中的寄存器进行写入传输，并以错误结束。

公开(公告)号：US20160282898A1

公开(公告)日：2016-09-29

申请号：US15172661

申请日：2016-06-03

Applicant: Atmel Corporation

Inventor： Sebastien Jouin ,  Patrice Menard ,  Thierry Gourbilleau ,  Yann Le Floch ,  Mohamed Aichouchi

IPC: G06F1/06

CPC classification number: G06F1/06 ,  G06F1/10 ,  G06F1/3237 ,  G06F2217/62 ,  H03K19/0016 ,  Y02D10/128

Abstract: A clock generation system for an integrated circuit (IC) chip (e.g., a microcontroller) is disclosed that allows digital blocks and other components in the IC chip to start and stop internal clocks dynamically on demand to reduce power consumption.

Abstract translation: 公开了用于集成电路（IC）芯片（例如，微控制器）的时钟发生系统，其允许IC芯片中的数字模块和其他组件根据需要动态地启动和停止内部时钟以降低功耗。

公开(公告)号：US09405720B2

公开(公告)日：2016-08-02

申请号：US13941671

申请日：2013-07-15

Applicant: Atmel Corporation

Inventor： Frode Milch Pedersen ,  Sebastien Jouin ,  Ian Fullerton

IPC: G06F13/42 ,  G06F13/16

CPC classification number: G06F3/0611 ,  G06F3/0655 ,  G06F3/0679 ,  G06F13/1689 ,  G06F13/4217 ,  G06F13/4243 ,  Y02D10/14 ,  Y02D10/151

Abstract: A latch signal is received from a non-volatile memory device that is indicative of a current access time for the non-volatile memory device. The access time represents an amount of time required for the non-volatile memory device to make data available responsive to a request for data. A bus system clock signal is received. The latch signal is evaluated and a wait state for the non-volatile memory device is adjusted based on the evaluation. The wait state represents a number of cycles of the bus system clock used by a central processing unit for an access of the non-volatile memory device. A bus system data ready signal that is triggered based on the adjusted wait state is produced. The bus system data ready signal, when triggered, indicates that data is available responsive to the request.

Abstract translation: 从非易失性存储器件接收指示非易失性存储器件的当前访问时间的锁存信号。 访问时间表示非易失性存储器件根据数据请求使数据可用的时间量。 接收总线系统时钟信号。 评估锁存信号，并且基于评估来调整非易失性存储器件的等待状态。 等待状态表示由中央处理单元用于访问非易失性存储器件的总线系统时钟的周期数。 产生基于调整后的等待状态触发的总线系统数据就绪信号。 当触发时，总线系统数据就绪信号表示响应于该请求可用数据。

公开(公告)号：US20170083075A1

公开(公告)日：2017-03-23

申请号：US15368808

申请日：2016-12-05

Applicant: Atmel Corporation

Inventor： Sebastien Jouin ,  Romain Oddoart ,  Patrice Menard ,  Mickael Le Dily ,  Thierry Gourbilleau

IPC: G06F1/32 ,  G06F13/16

CPC classification number: G06F1/3243 ,  G06F1/3287 ,  G06F13/1673 ,  Y02D10/152

Abstract: A microcontroller is operable in a low-power mode and includes one or more I/O connectors, as well as an I/O controller operable to provide control signals for controlling a state of a particular one of the I/O connectors. The I/O controller is powered off or deactivated during the low-power mode. The microcontroller also includes I/O connector state control logic operable to control the state of the particular one of the I/O connectors in accordance with the control signals from the I/O controller. The I/O connector state control logic includes I/O connector state retention logic that retains states of the control signals and maintains the particular I/O connector in a corresponding state in accordance with the retained control signals while the microcontroller is in the low-power mode.

公开(公告)号：US09442873B2

公开(公告)日：2016-09-13

申请号：US14510529

申请日：2014-10-09

Applicant: Atmel Corporation

Inventor： Laurentiu Birsan ,  Frode Milch Pedersen ,  Nicolas Graffet ,  Stein Danielsen ,  Sebastien Jouin

IPC: G06F13/28 ,  G01R31/08

CPC classification number: G06F13/28

Abstract: Systems and methods for direct memory access are described. One example system includes a memory module that includes a first memory portion that maintains transfer descriptors of direct memory access (DMA) channels, and a second memory portion that maintains transfer descriptors of enabled DMA channels. The system includes a controller coupled to the memory module, the controller includes one or more DMA channels coupled to a system bus, a channel arbiter that selects one of the enabled DMA channels as an active DMA channel for data transfer including re-arbitrating after each burst or beat in a given transfer, and an active channel buffer that receives a transfer descriptor of the active DMA channel from the second memory portion. The controller is configured to write back the transfer descriptor of the active DMA channel into the second memory portion when the active DMA channel loses arbitration.

Abstract translation: 描述用于直接存储器访问的系统和方法。 一个示例系统包括存储器模块，该存储器模块包括保持直接存储器访问（DMA）通道的传送描述符的第一存储器部分和维持已使能的DMA通道的传送描述符的第二存储器部分。 该系统包括耦合到存储器模块的控制器，控制器包括耦合到系统总线的一个或多个DMA通道，通道仲裁器，其选择使能的DMA通道中的一个作为用于数据传输的活动DMA通道，包括在每一个之后重新仲裁 在给定传送中突发或跳动，以及从第二存储器部分接收活动DMA通道的传输描述符的活动通道缓冲器。 控制器被配置为当活动DMA通道失去仲裁时将有效DMA通道的传输描述符写回第二存储器部分。

公开(公告)号：US09213397B2

公开(公告)日：2015-12-15

申请号：US13788366

申请日：2013-03-07

Applicant: Atmel Corporation

Inventor： Sebastien Jouin ,  Romain Oddoart ,  Patrice Menard ,  Mickael Le Dily ,  Thierry Gourbilleau

IPC: G06F1/32

CPC classification number: G06F1/3243 ,  G06F1/3296 ,  Y02D10/152 ,  Y02D10/172

Abstract: A microcontroller system can operate in a number of power modes. In response to changing from a previous mode to a present mode, the microcontroller system reads a present calibration value correspond to the present mode from system configuration storage and write the present calibration value to a configuration register for a component. A logic block for the component reads the present calibration value and calibrates the component.

Abstract translation: 微控制器系统可以在多种功率模式下工作。 响应于从先前模式变为当前模式，微控制器系统从系统配置存储读取对应于当前模式的当前校准值，并将当前校准值写入组件的配置寄存器。 组件的逻辑块读取当前校准值并校准组件。

公开(公告)号：US09146887B2

公开(公告)日：2015-09-29

申请号：US13692531

申请日：2012-12-03

Applicant: Atmel Corporation

Inventor： Sebastien Jouin ,  Sylvain Garnier ,  Thierry Delalande ,  Romain Oddoart

IPC: G06F3/00 ,  G09G3/36 ,  G06F13/32

CPC classification number: G06F13/32 ,  G06F13/4234 ,  G09G3/36

Abstract: A device comprises a central processing unit (CPU), a display controller configured for controlling a digital display and a memory configured for storing data corresponding to the digital display. The device includes a direct memory access (DMA) controller configured for autonomously transferring the data from the memory directly to the display controller without CPU intervention.

Abstract translation: 一种设备包括中央处理单元（CPU），被配置为用于控制数字显示器的显示控制器和被配置为存储对应于数字显示器的数据的存储器。 该设备包括直接存储器访问（DMA）控制器，其被配置为在没有CPU干预的情况下将数据从存储器自动地直接传送到显示器控制器。

公开(公告)号：US20150253839A1

公开(公告)日：2015-09-10

申请号：US14716983

申请日：2015-05-20

Applicant: Atmel Corporation

Inventor： Sebastien Jouin ,  Romain Oddoart ,  Patrice Menard ,  Mickael Le Dily ,  Thierry Gourbilleau

IPC: G06F1/32

CPC classification number: G06F1/3243 ,  G06F1/3287 ,  G06F13/1673 ,  Y02D10/152

Abstract: A microcontroller is operable in a low-power mode and includes one or more I/O connectors, as well as an I/O controller operable to provide control signals for controlling a state of a particular one of the I/O connectors. The I/O controller is powered off or deactivated during the low-power mode. The microcontroller also includes I/O connector state control logic operable to control the state of the particular one of the I/O connectors in accordance with the control signals from the I/O controller. The I/O connector state control logic includes I/O connector state retention logic that retains states of the control signals and maintains the particular I/O connector in a corresponding state in accordance with the retained control signals while the microcontroller is in the low-power mode.

Abstract translation: 微控制器在低功率模式下可操作并且包括一个或多个I / O连接器，以及I / O控制器，其可操作以提供用于控制I / O连接器中特定一个的状态的控制信号。 在低功耗模式下，I / O控制器关闭或关闭。 微控制器还包括I / O连接器状态控制逻辑，其可操作以根据来自I / O控制器的控制信号来控制特定I / O连接器的状态。 I / O连接器状态控制逻辑包括I / O连接器状态保持逻辑，其保持控制信号的状态，并且在微控制器处于低电平状态时，根据保留的控制信号将特定的I / O连接器保持在相应的状态， 电源模式。

公开(公告)号：US08880756B1

公开(公告)日：2014-11-04

申请号：US13932925

申请日：2013-07-01

Applicant: Atmel Corporation

Inventor： Laurentiu Birsan ,  Frode Milch Pedersen ,  Nicolas Graffet ,  Stein Danielsen ,  Sebastien Jouin

IPC: G06F13/28 ,  G01R31/08

CPC classification number: G06F13/28

Abstract: Systems and methods for direct memory access are described. One example system includes a memory module that includes a first memory portion that maintains transfer descriptors of direct memory access (DMA) channels, and a second memory portion that maintains transfer descriptors of enabled DMA channels. The system includes a controller coupled to the memory module, the controller includes one or more DMA channels coupled to a system bus, a channel arbiter that selects one of the enabled DMA channels as an active DMA channel for data transfer including re-arbitrating after each burst or beat in a given transfer, and an active channel buffer that receives a transfer descriptor of the active DMA channel from the second memory portion. The controller is configured to write back the transfer descriptor of the active DMA channel into the second memory portion when the active DMA channel loses arbitration.

Abstract translation: 描述用于直接存储器访问的系统和方法。 一个示例系统包括存储器模块，该存储器模块包括保持直接存储器访问（DMA）通道的传送描述符的第一存储器部分和维持已使能的DMA通道的传送描述符的第二存储器部分。 该系统包括耦合到存储器模块的控制器，控制器包括耦合到系统总线的一个或多个DMA通道，通道仲裁器，其选择使能的DMA通道中的一个作为用于数据传输的活动DMA通道，包括在每一个之后重新仲裁 在给定传送中突发或跳动，以及从第二存储器部分接收活动DMA通道的传输描述符的活动通道缓冲器。 控制器被配置为当活动DMA通道失去仲裁时将有效DMA通道的传输描述符写回第二存储器部分。