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    Method and structure for low resistive source and drain regions in a replacement metal gate process flow
    11.
    发明授权
    Method and structure for low resistive source and drain regions in a replacement metal gate process flow 有权
    替代金属栅极工艺流程中低电阻源极和漏极区域的方法和结构

    公开(公告)号：US08432002B2

    公开(公告)日：2013-04-30

    申请号：US13170565

    申请日：2011-06-28

    申请人： Balasubramanian S. Haran ,  Kangguo Cheng ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

    发明人： Balasubramanian S. Haran ,  Kangguo Cheng ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

    IPC分类号： H01L29/72

    CPC分类号： H01L21/84 ,  H01L21/22 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

    摘要： In one embodiment a method is provided that includes providing a structure including a semiconductor substrate having at least one device region located therein, and a doped semiconductor layer located on an upper surface of the semiconductor substrate in the at least one device region. After providing the structure, a sacrificial gate region having a spacer located on sidewalls thereof is formed on an upper surface of the doped semiconductor layer. A planarizing dielectric material is then formed and the sacrificial gate region is removed to form an opening that exposes a portion of the doped semiconductor layer. The opening is extended to an upper surface of the semiconductor substrate and then an anneal is performed that causes outdiffusion of dopant from remaining portions of the doped semiconductor layer forming a source region and a drain region in portions of the semiconductor substrate that are located beneath the remaining portions of the doped semiconductor layer. A high k gate dielectric and a metal gate are then formed into the extended opening.

    摘要翻译： 在一个实施例中，提供了一种方法，其包括提供包括其中位于其中的至少一个器件区域的半导体衬底的结构以及位于所述至少一个器件区域中的半导体衬底的上表面上的掺杂半导体层。 在提供结构之后，在掺杂半导体层的上表面上形成具有位于其侧壁上的间隔物的牺牲栅极区。 然后形成平坦化电介质材料，去除牺牲栅极区域以形成露出掺杂半导体层的一部分的开口。 开口延伸到半导体衬底的上表面，然后执行退火，其导致掺杂剂的剩余部分在掺杂半导体层的剩余部分中形成源区域和漏极区域，半导体衬底的位于第 掺杂半导体层的剩余部分。 然后，将高k栅极电介质和金属栅极形成为延伸的开口。

    Method and Structure for Low Resistive Source and Drain Regions in a Replacement Metal Gate Process Flow
    12.
    发明申请
    Method and Structure for Low Resistive Source and Drain Regions in a Replacement Metal Gate Process Flow 有权
    替代金属栅极工艺流程中低电阻源极和漏极区域的方法和结构

    公开(公告)号：US20130001706A1

    公开(公告)日：2013-01-03

    申请号：US13170565

    申请日：2011-06-28

    申请人： Balasubramanian S. Haran ,  Kangguo Cheng ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

    发明人： Balasubramanian S. Haran ,  Kangguo Cheng ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

    IPC分类号： H01L29/78 ,  H01L21/8238 ,  H01L21/336

    CPC分类号： H01L21/84 ,  H01L21/22 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

    摘要： In one embodiment a method is provided that includes providing a structure including a semiconductor substrate having at least one device region located therein, and a doped semiconductor layer located on an upper surface of the semiconductor substrate in the at least one device region. After providing the structure, a sacrificial gate region having a spacer located on sidewalls thereof is formed on an upper surface of the doped semiconductor layer. A planarizing dielectric material is then formed and the sacrificial gate region is removed to form an opening that exposes a portion of the doped semiconductor layer. The opening is extended to an upper surface of the semiconductor substrate and then an anneal is performed that causes outdiffusion of dopant from remaining portions of the doped semiconductor layer forming a source region and a drain region in portions of the semiconductor substrate that are located beneath the remaining portions of the doped semiconductor layer. A high k gate dielectric and a metal gate are then formed into the extended opening.

    摘要翻译： 在一个实施例中，提供了一种方法，其包括提供包括其中位于其中的至少一个器件区域的半导体衬底的结构以及位于所述至少一个器件区域中的半导体衬底的上表面上的掺杂半导体层。 在提供结构之后，在掺杂半导体层的上表面上形成具有位于其侧壁上的间隔物的牺牲栅极区。 然后形成平坦化电介质材料，去除牺牲栅极区域以形成露出掺杂半导体层的一部分的开口。 开口延伸到半导体衬底的上表面，然后执行退火，其导致掺杂剂的剩余部分在掺杂半导体层的剩余部分中形成源区域和漏极区域，半导体衬底的位于第 掺杂半导体层的剩余部分。 然后，将高k栅极电介质和金属栅极形成为延伸的开口。

    UNDERCUT INSULATING REGIONS FOR SILICON-ON-INSULATOR DEVICE
    14.
    发明申请
    UNDERCUT INSULATING REGIONS FOR SILICON-ON-INSULATOR DEVICE 有权
    用于绝缘体绝缘体器件的绝缘绝缘区域

    公开(公告)号：US20140001555A1

    公开(公告)日：2014-01-02

    申请号：US13537141

    申请日：2012-06-29

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/0649 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/41766 ,  H01L29/78 ,  H01L29/7838

    摘要： A method of making a silicon-on-insulator (SOI) semiconductor device includes etching an undercut isolation trench into an SOI substrate, the SOI substrate comprising a bottom substrate, a buried oxide (BOX) layer formed on the bottom substrate, and a top SOI layer formed on the BOX layer, wherein the undercut isolation trench extends through the top SOI layer and the BOX layer and into the bottom substrate such that a portion of the undercut isolation trench is located in the bottom substrate underneath the BOX layer. The undercut isolation trench is filled with an undercut fill comprising an insulating material to form an undercut isolation region. A field effect transistor (FET) device is formed on the top SOI layer adjacent to the undercut isolation region, wherein the undercut isolation region extends underneath a source/drain region of the FET.

    摘要翻译： 制造绝缘体上硅（SOI）半导体器件的方法包括将底切隔离沟槽蚀刻成SOI衬底，所述SOI衬底包括底部衬底，形成在底部衬底上的掩埋氧化物（BOX）层，以及顶部 SOI层，其形成在BOX层上，其中底切隔离沟槽延伸穿过顶部SOI层和BOX层并进入底部衬底，使得底切绝缘沟槽的一部分位于BOX层下方的底部衬底中。 底切隔离槽填充有包括绝缘材料的底切填充物以形成底切隔离区域。 在与底切隔离区相邻的顶部SOI层上形成场效应晶体管（FET）器件，其中底切隔离区延伸在FET的源极/漏极区的下方。

    Undercut insulating regions for silicon-on-insulator device
    15.
    发明授权
    Undercut insulating regions for silicon-on-insulator device 有权
    用于绝缘体上硅器件的底切绝缘区域

    公开(公告)号：US09214378B2

    公开(公告)日：2015-12-15

    申请号：US13537141

    申请日：2012-06-29

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

    IPC分类号： H01L21/84 ,  H01L21/762 ,  H01L27/12

    CPC分类号： H01L29/0649 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/41766 ,  H01L29/78 ,  H01L29/7838

    摘要： A method of making a silicon-on-insulator (SOI) semiconductor device includes etching an undercut isolation trench into an SOI substrate, the SOI substrate comprising a bottom substrate, a buried oxide (BOX) layer formed on the bottom substrate, and a top SOI layer formed on the BOX layer, wherein the undercut isolation trench extends through the top SOI layer and the BOX layer and into the bottom substrate such that a portion of the undercut isolation trench is located in the bottom substrate underneath the BOX layer. The undercut isolation trench is filled with an undercut fill comprising an insulating material to form an undercut isolation region. A field effect transistor (FET) device is formed on the top SOI layer adjacent to the undercut isolation region, wherein the undercut isolation region extends underneath a source/drain region of the FET.

    摘要翻译： 制造绝缘体上硅（SOI）半导体器件的方法包括将底切隔离沟槽蚀刻成SOI衬底，所述SOI衬底包括底部衬底，形成在底部衬底上的掩埋氧化物（BOX）层，以及顶部 SOI层，其形成在BOX层上，其中底切隔离沟槽延伸穿过顶部SOI层和BOX层并进入底部衬底，使得底切绝缘沟槽的一部分位于BOX层下方的底部衬底中。 底切隔离槽填充有包括绝缘材料的底切填充物以形成底切隔离区域。 在与底切隔离区相邻的顶部SOI层上形成场效应晶体管（FET）器件，其中底切隔离区延伸在FET的源极/漏极区的下方。

    Bulk fin-field effect transistors with well defined isolation
    18.
    发明授权
    Bulk fin-field effect transistors with well defined isolation 有权
    散装场效应晶体管具有明确的隔离

    公开(公告)号：US08420459B1

    公开(公告)日：2013-04-16

    申请号：US13277956

    申请日：2011-10-20

    申请人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

    发明人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

    IPC分类号： H01L21/00 ,  H01L21/84

    CPC分类号： H01L29/66795 ,  H01L21/02518 ,  H01L21/02636 ,  H01L21/265 ,  H01L29/66477 ,  H01L29/6681 ,  H01L29/785

    摘要： A fin field-effect-transistor fabricated by forming a dummy fin structure on a semiconductor substrate. A dielectric layer is formed on the semiconductor substrate. The dielectric layer surrounds the dummy fin structure. The dummy fin structure is removed to form a cavity within the dielectric layer. The cavity exposes a portion of the semiconductor substrate thereby forming an exposed portion of the semiconductor substrate within the cavity. A dopant is implanted into the exposed portion of the semiconductor substrate within the cavity thereby creating a dopant implanted exposed portion of the semiconductor substrate within the cavity. A semiconductor layer is epitaxially grown within the cavity atop the dopant implanted exposed portion of the semiconductor substrate.

    摘要翻译： 通过在半导体衬底上形成虚拟鳍结构制造的鳍状场效晶体管。 在半导体衬底上形成电介质层。 电介质层围绕虚拟翅片结构。 去除虚拟翅片结构以在电介质层内形成空腔。 空腔暴露半导体衬底的一部分，从而在腔内形成半导体衬底的暴露部分。 将掺杂剂注入到空腔内的半导体衬底的暴露部分中，从而在腔内形成掺杂剂注入的半导体衬底的暴露部分。 在半导体衬底的掺杂剂注入的暴露部分的顶部的腔内外延生长半导体层。

    MOSFET INCLUDING ASYMMETRIC SOURCE AND DRAIN REGIONS
    19.
    发明申请
    MOSFET INCLUDING ASYMMETRIC SOURCE AND DRAIN REGIONS 失效
    MOSFET包括不对称源和漏极区

    公开(公告)号：US20130049115A1

    公开(公告)日：2013-02-28

    申请号：US13216554

    申请日：2011-08-24

    申请人： KANGGUO CHENG ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

    发明人： KANGGUO CHENG ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/66477 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/84 ,  H01L29/66045 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/66803 ,  H01L29/785

    摘要： At least one drain-side surfaces of a field effect transistor (FET) structure, which can be a structure for a planar FET or a fin FET, is structurally damaged by an angled ion implantation of inert or electrically active dopants, while at least one source-side surface of the transistor is protected from implantation by a gate stack and a gate spacer. Epitaxial growth of a semiconductor material is retarded on the at least one structurally damaged drain-side surface, while epitaxial growth proceeds without retardation on the at least one source-side surface. A raised epitaxial source region has a greater thickness than a raised epitaxial drain region, thereby providing an asymmetric FET having lesser source-side external resistance than drain-side external resistance, and having lesser drain-side overlap capacitance than source-side overlap capacitance.

    摘要翻译： 作为平面FET或鳍式FET的结构的场效应晶体管（FET）结构的至少一个漏极侧表面在结构上被惰性或电活性掺杂剂的成角度的离子注入损坏，而至少一个 保护晶体管的源极侧表面不被栅极堆叠和栅极间隔物的注入。 半导体材料的外延生长在至少一个结构损坏的漏极侧表面上延迟，而外延生长在至少一个源极侧表面上没有延迟。 凸起的外延源区域具有比凸起的外延漏极区域更大的厚度，从而提供具有比漏极侧外部电阻更小的源极侧外部电阻并且具有比源极重叠电容更少的漏极侧重叠电容的非对称FET。

    Method to improve wet etch budget in FEOL integration
    20.
    发明授权
    Method to improve wet etch budget in FEOL integration 失效
    在FEOL集成中改善湿法蚀刻预算的方法

    公开(公告)号：US08679941B2

    公开(公告)日：2014-03-25

    申请号：US13422138

    申请日：2012-03-16

    申请人： Jason E Cummings ,  Lisa F Edge ,  Balasubramanian S. Haran ,  David V Horak ,  Hemanth Jagannathan ,  Sanjay Mehta

    发明人： Jason E Cummings ,  Lisa F Edge ,  Balasubramanian S. Haran ,  David V Horak ,  Hemanth Jagannathan ,  Sanjay Mehta

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76229

    摘要： A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 Å-100 Å) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfOx, AlyOx, ZrOx, HfZrOx, and HfSiOx. The inventive wet etch resistant layer improves the wet etch budget of subsequent wet etch processing steps.

    摘要翻译： 提供一种形成半导体器件的方法，其中在一个实施例中，STI填充物在衬垫氮化物和衬垫氧化物层下方凹入到与衬底的顶表面基本上共面的水平。 至少形成凹入的STI填充材料的上表面，形成薄（具有在约10埃-120埃范围内的厚度）耐湿蚀刻层。 薄的耐湿蚀刻层比至少衬垫氧化物层更耐湿蚀刻工艺。 薄的耐湿蚀刻层可以是耐火电介质材料，或诸如HfO x，Al y O x，ZrO x，HfZrO x和HfSiO x的电介质。 本发明的耐湿蚀刻层提高了后续湿蚀刻处理步骤的湿法蚀刻预算。