公开(公告)号：US20050286284A1

公开(公告)日：2005-12-29

申请号：US10882005

申请日：2004-06-29

申请人： Sun-Teck See ,  Horng-Yee Chou ,  Charles Lee

发明人： Sun-Teck See ,  Horng-Yee Chou ,  Charles Lee

IPC分类号： G11C5/00 ,  G11C11/34 ,  G11C16/02

CPC分类号： G11C16/02

摘要： Through the use of an allocation logic unit with a Flash controller, a single primary chip enable is de-multiplexed into a multiple secondary chip enables for multiple Flash memory dies or chips. In so doing, Flash storage device capacity is greatly expanded. In a first aspect, a memory package includes a plurality of memories; and an allocation logic unit coupled to the plurality of memories for receiving a single chip enable signal. The allocation logic unit de-multiplexes the single chip enable signal to a plurality of chip enable signals. Each of the plurality of chip enable signals access to one of the plurality of memories. In a second aspect, a printed circuit board (PCB) includes a Flash controller for providing at least one primary chip enable signal. The PCB also includes a plurality of Flash memory chips and at least one allocation logic unit coupled to at least a portion of the plurality of Flash memory chips and the Flash controller. The allocation logic unit receives the at least one chip enable signal and de-multiplexes the at least one chip enable signal to a plurality of secondary chip enable signals. Each of the plurality of chip enable signals controls access to one of the Flash memory chips.

摘要翻译： 通过使用具有闪存控制器的分配逻辑单元，单个主芯片使能被解复用到多个次级芯片中，使得能够用于多个闪存芯片或芯片。 这样做，Flash存储设备容量大大扩大。 在第一方面，一种存储器包括多个存储器; 以及耦合到所述多个存储器以用于接收单个芯片使能信号的分配逻辑单元。 分配逻辑单元将单芯片使能信号解复用到多个芯片使能信号。 多个芯片使能信号中的每一个访问多个存储器中的一个。 在第二方面，印刷电路板（PCB）包括用于提供至少一个主芯片使能信号的闪光控制器。 PCB还包括多个闪存芯片和耦合到多个闪存芯片和闪存控制器的至少一部分的至少一个分配逻辑单元。 所述分配逻辑单元接收所述至少一个芯片使能信号，并且将所述至少一个芯片使能信号解复用到多个次级芯片使能信号。 多个芯片使能信号中的每一个控制对闪存芯片之一的访问。

公开(公告)号：US20050285248A1

公开(公告)日：2005-12-29

申请号：US10881203

申请日：2004-06-29

申请人： Sun-Teck See ,  Horng-Yee Chou ,  Charles Lee

发明人： Sun-Teck See ,  Horng-Yee Chou ,  Charles Lee

IPC分类号： G11C5/04 ,  H01L23/02 ,  H01L23/495 ,  H01L23/50 ,  H01L25/10 ,  H05K1/18

CPC分类号： G11C5/04 ,  H01L23/49575 ,  H01L23/50 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/181 ,  H05K1/181 ,  H05K2201/10515 ,  H05K2201/10689 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A memory package and a chip architecture which includes stacked multiple memory chips is described. In a first aspect, a memory package comprises a substrate and a plurality of memory dies mounted on the substrate. Each die has a separate chip enable. In a second aspect, a chip architecture comprises a printed circuit board (PCB). The PCB includes a footprint. The footprint includes at least one no connect (NC) pad. The chip architecture includes a plurality of stacked memory chips mounted on the printed circuit board. Each of the plurality of stacked memory has a chip enable signal pin and also has at least one NC pin. At least one of the plurality of stacked memory chips utilizes an NC pin of another of the stacked memory chips to route the chip enable pin to at least one NC pad of the footprint. Accordingly, a system and method in accordance with the present invention provides for increased memory density within a particular space constraint by (1) providing multiple dies in a single memory package and (2) by providing stacked memory chips in a single PCB footprint. In so doing, the package/PCB will have increased memory density over a conventional package/PCB within the same space constraints, and the capacity of Flash storage devices is expanded accordingly.

摘要翻译： 描述了包括堆叠的多个存储器芯片的存储器封装和芯片架构。 在第一方面，一种存储器封装包括衬底和安装在衬底上的多个存储器管芯。 每个管芯都有独立的芯片使能。 在第二方面，芯片架构包括印刷电路板（PCB）。 PCB包括一个占位面积。 足迹包括至少一个无连接（NC）垫。 芯片架构包括安装在印刷电路板上的多个堆叠的存储器芯片。 多个堆叠存储器中的每一个具有芯片使能信号引脚，并且还具有至少一个NC引脚。 多个层叠的存储器芯片中的至少一个利用另一个堆叠的存储器芯片的NC引脚将芯片使能引脚路由到占用空间的至少一个NC焊盘。 因此，根据本发明的系统和方法通过（1）在单个存储器封装中提供多个管芯并且（2）通过在单个PCB封装中提供堆叠的存储器芯片来提供特定空间约束内的增加的存储器密度。 在这样做的同时，封装/ PCB将在相同的空间限制内在传统封装/ PCB上增加存储密度，并相应地扩展闪存存储设备的容量。

公开(公告)号：US20050251609A1

公开(公告)日：2005-11-10

申请号：US10839648

申请日：2004-05-04

申请人： Horng-Yee Chou ,  Sun-Teck See

发明人： Horng-Yee Chou ,  Sun-Teck See

IPC分类号： G06F3/00 ,  G06F13/40

CPC分类号： G06F13/4081 ,  G06F2213/0026 ,  G06F2213/0042

摘要： A peripheral device coupleable to an ExpressCard™ interface of a host system includes an ExpressCard™ portion and a second portion coupleable to the ExpressCard™ portion. Functionality of the peripheral device is partitioned between the ExpressCard™ portion and the second portion.

摘要翻译： 可耦合到主机系统的ExpressCard TM接口的外围设备包括ExpressCard TM部分和可连接到ExpressCard TM部分的第二部分。 外围设备的功能在ExpressCard TM部分和第二部分之间分配。

公开(公告)号：US07849242B2

公开(公告)日：2010-12-07

申请号：US12254428

申请日：2008-10-20

申请人： Charles C. Lee ,  Sun-Teck See ,  Horng-Yee Chou ,  I-pieng Peter Kao

发明人： Charles C. Lee ,  Sun-Teck See ,  Horng-Yee Chou ,  I-pieng Peter Kao

IPC分类号： G06F3/00 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F13/1684 ,  G11C13/0004 ,  G11C16/102 ,  G11C2216/30

摘要： A PCI Express-compatible flash device can include one or more flash memory modules, a controller, and an ExpressCard interface. The controller can advantageously provide PCI Express functionality as well as flash memory operations, e.g. writing, reading, or erasing, using the ExpressCard interface. A PIO interface includes sending first and second memory request packets to the flash device. The first memory request packet includes a command word setting that prepares the flash device for the desired operation. The second memory request packet triggers the operation and includes a data payload, if needed. A DMA interface includes sending the second memory request from the flash device to the host, thereby triggering the host to release the system bus for the DMA operation.

摘要翻译： 兼容PCI Express的闪存设备可以包括一个或多个闪存模块，控制器和ExpressCard接口。 控制器可以有利地提供PCI Express功能以及闪速存储器操作，例如， 使用ExpressCard接口进行写入，读取或擦除。 PIO接口包括向闪存设备发送第一和第二存储器请求包。 第一存储器请求分组包括为所需操作准备闪存设备的命令字设置。 如果需要，第二存储器请求分组触发操作并且包括数据有效载荷。 DMA接口包括将第二存储器请求从闪存设备发送到主机，从而触发主机释放用于DMA操作的系统总线。

公开(公告)号：US07243185B2

公开(公告)日：2007-07-10

申请号：US10818653

申请日：2004-04-05

申请人： Sun-Teck See ,  Tzu-Yih Chu ,  Horng-Yee Chou ,  Charles C. Lee

发明人： Sun-Teck See ,  Tzu-Yih Chu ,  Horng-Yee Chou ,  Charles C. Lee

IPC分类号： G06F12/00

CPC分类号： G06F13/161 ,  G06F12/0804 ,  G06F2212/2022 ,  G11C7/1015 ,  G11C2211/5641

摘要： A multi media card (MMC) is disclosed. The MMC includes a flash controller and at least one flash memory device. The flash controller increases the throughput of the at least one flash memory device to match the speed of a host bus coupled to the MMC. The flash controller increases the throughput by performing one or more of performing a read-ahead memory read operation, performing a write-ahead memory write operation, increasing the size of a page register of the at least one flash memory device, increasing the width of a memory data bus, performing a dual-channel concurrent memory read operation, performing a dual-channel concurrent memory write operation, performing a write-cache memory write operation, and any combination thereof.

摘要翻译： 公开了一种多媒体卡（MMC）。 MMC包括闪存控制器和至少一个闪存设备。 闪存控制器增加至少一个闪存设备的吞吐量以匹配耦合到MMC的主机总线的速度。 闪存控制器通过执行执行预读存储器读取操作，执行写入预先存储器写入操作，增加至少一个闪速存储器件的页面寄存器的大小中的一个或多个来增加吞吐量， 存储器数据总线，执行双通道并行存储器读取操作，执行双通道并行存储器写入操作，执行写入 - 高速缓冲存储器写入操作及其任何组合。

公开(公告)号：US20050286283A1

公开(公告)日：2005-12-29

申请号：US10881037

申请日：2004-06-29

申请人： Sun-Teck See ,  Horng-Yee Chou ,  Charles Lee

发明人： Sun-Teck See ,  Horng-Yee Chou ,  Charles Lee

IPC分类号： G11C5/00 ,  G11C5/06 ,  G11C16/02 ,  H05K1/18

CPC分类号： G11C16/02 ,  G06K19/077 ,  G06K19/07732 ,  H05K1/181

摘要： A Flash storage device is disclosed. The Flash storage device comprises a plurality of memories and a printed circuit board coupled to the plurality of memories. The PCB is extended beyond a predetermined dimension to accommodate the plurality of memories. By extending the length and/or the width of the PCB, additional memories can be added to the PCB, thereby adding to the memory capacity of the device.

摘要翻译： 闪存存储设备被公开。 闪存存储设备包括多个存储器和耦合到多个存储器的印刷电路板。 PCB延伸超过预定尺寸以容纳多个存储器。 通过延长PCB的长度和/或宽度，可以向PCB添加额外的存储器，从而增加了设备的存储容量。

公开(公告)号：US20050223158A1

公开(公告)日：2005-10-06

申请号：US10818653

申请日：2004-04-05

申请人： Sun-Teck See ,  Tzu-Yih Chu ,  Horng-Yee Chou ,  Charles Lee

发明人： Sun-Teck See ,  Tzu-Yih Chu ,  Horng-Yee Chou ,  Charles Lee

IPC分类号： G06F12/00 ,  G06F13/16 ,  G11C7/10

CPC分类号： G06F13/161 ,  G06F12/0804 ,  G06F2212/2022 ,  G11C7/1015 ,  G11C2211/5641

摘要： A multi media card (MMC) is disclosed. The MMC includes a flash controller and at least one flash memory device. The flash controller increases the throughput of the at least one flash memory device to match the speed of a host bus coupled to the MMC. The flash controller increases the throughput by performing one or more of performing a read-ahead memory read operation, performing a write-ahead memory write operation, increasing the size of a page register of the at least one flash memory device, increasing the width of a memory data bus, performing a dual-channel concurrent memory read operation, performing a dual-channel concurrent memory write operation, performing a write-cache memory write operation, and any combination thereof.

摘要翻译： 公开了一种多媒体卡（MMC）。 MMC包括闪存控制器和至少一个闪存设备。 闪存控制器增加至少一个闪存设备的吞吐量以匹配耦合到MMC的主机总线的速度。 闪存控制器通过执行执行预读存储器读取操作，执行写入预先存储器写入操作，增加至少一个闪速存储器件的页面寄存器的大小中的一个或多个来增加吞吐量， 存储器数据总线，执行双通道并行存储器读取操作，执行双通道并行存储器写入操作，执行写入 - 高速缓冲存储器写入操作及其任何组合。

公开(公告)号：US06874044B1

公开(公告)日：2005-03-29

申请号：US10605140

申请日：2003-09-10

申请人： Horng-Yee Chou ,  Sun-Teck See ,  Tzu-Yih Chu

发明人： Horng-Yee Chou ,  Sun-Teck See ,  Tzu-Yih Chu

IPC分类号： G06F3/00 ,  G06F3/06 ,  G06F13/00 ,  G06F13/12 ,  G06F13/38 ,  G11C16/10

CPC分类号： G06F13/387 ,  G11C16/102

摘要： A flash-drive or flash-card reader connects to a personal computer (PC) through a serial link such as a Universal-Serial-Bus (USB), IEEE 1394, SATA, or IDE. A local CPU acts as the bus master of a CPU bus that connects to slave ports on a flash-memory controller, a serial engine, and a RAM buffer. A second bus in parallel to the CPU bus connects a second slave port on the RAM buffer to a master port on the flash-memory controller and to a master port on the serial engine. The flash-memory controller or the serial engine can use their master ports to transfer data to and from the RAM buffer using the second bus, allowing the CPU to retain control of the CPU bus. The second bus is a flash-serial buffer bus that improves data transfer rates. The flash-memory controller can prefetch into the RAM buffer.

摘要翻译： 闪存驱动器或闪存卡读卡器通过串行链路（例如通用串行总线（USB），IEEE 1394，SATA或IDE）连接到个人计算机（PC）。 本地CPU作为连接闪存控制器，串行引擎和RAM缓冲区的从站端口的CPU总线的总线主机。 与CPU总线并行的第二个总线将RAM缓冲器上的第二个从站端口连接到闪存控制器上的主站和串行引擎上的主站。 闪存控制器或串行引擎可以使用其主端口使用第二个总线将数据传输到RAM缓冲区，并允许CPU保留对CPU总线的控制。 第二个总线是提供数据传输速率的闪存串行缓冲区总线。 闪存控制器可以预取入RAM缓冲区。

公开(公告)号：US20050055481A1

公开(公告)日：2005-03-10

申请号：US10605140

申请日：2003-09-10

申请人： Horng-Yee Chou ,  Sun-Teck See ,  Tzu-Yih Chu

发明人： Horng-Yee Chou ,  Sun-Teck See ,  Tzu-Yih Chu

IPC分类号： G06F3/00 ,  G06F3/06 ,  G06F13/00 ,  G06F13/12 ,  G06F13/38 ,  G11C16/10

CPC分类号： G06F13/387 ,  G11C16/102

摘要： A flash-drive or flash-card reader connects to a personal computer (PC) through a serial link such as a Universal-Serial-Bus (USB), IEEE 1394, SATA, or IDE. A local CPU acts as the bus master of a CPU bus that connects to slave ports on a flash-memory controller, a serial engine, and a RAM buffer. A second bus in parallel to the CPU bus connects a second slave port on the RAM buffer to a master port on the flash-memory controller and to a master port on the serial engine. The flash-memory controller or the serial engine can use their master ports to transfer data to and from the RAM buffer using the second bus, allowing the CPU to retain control of the CPU bus. The second bus is a flash-serial buffer bus that improves data transfer rates. The flash-memory controller can prefetch into the RAM buffer.

摘要翻译： 闪存驱动器或闪存卡读卡器通过串行链路（例如通用串行总线（USB），IEEE 1394，SATA或IDE）连接到个人计算机（PC）。 本地CPU作为连接闪存控制器，串行引擎和RAM缓冲区的从站端口的CPU总线的总线主机。 与CPU总线并行的第二个总线将RAM缓冲器上的第二个从站端口连接到闪存控制器上的主站和串行引擎上的主站。 闪存控制器或串行引擎可以使用其主端口使用第二个总线将数据传输到RAM缓冲区，并允许CPU保留对CPU总线的控制。 第二个总线是提供数据传输速率的闪存串行缓冲区总线。 闪存控制器可以预取入RAM缓冲区。

公开(公告)号：US06993618B2

公开(公告)日：2006-01-31

申请号：US10707835

申请日：2004-01-15

申请人： Ben Wei Chen ,  Tzu-Yih Chu ,  Sun-Teck See

发明人： Ben Wei Chen ,  Tzu-Yih Chu ,  Sun-Teck See

IPC分类号： G06F13/00 ,  G06F1/16

CPC分类号： G06F3/08

摘要： A flash-card exchanger has two modes of operation. When a host personal computer (PC) is connected to a Universal-Serial-Bus (USB) connector, the flash-card exchanger operates in a card reader mode, allowing the host to read data from removable flash-memory cards inserted into connector slots of the flash-card exchanger. When the host PC is not connected, a USB flash-memory thumb or key-chain drive can be inserted into a second USB connector. A USB dual-mode microcontroller acts as a USB host, reading data from the removable flash-memory card and writing the data to the USB-memory key drive using USB packets. Since the USB-memory key drive is small and removable, the user can upgrade to larger storage capacities by plugging in a larger-capacity USB-memory key drive. A flash-exchanger program executing on the USB dual-mode microcontroller copies data from an input-output bus and generates USB packets to the USB-memory key drive.

摘要翻译： 闪存卡交换机有两种操作模式。 当主机个人计算机（PC）连接到通用串行总线（USB）连接器时，闪存卡交换器以读卡器模式运行，允许主机从插入连接器插槽的可移动闪存卡读取数据 的闪存卡交换机。 当主机未连接时，可以将USB闪存拇指或键盘驱动器插入第二个USB连接器。 USB双模微控制器充当USB主机，从可移动闪存卡读取数据，并使用USB数据包将数据写入USB存储器键盘驱动器。 由于USB存储器按键驱动器小巧且可移动，因此用户可以通过插入更大容量的USB存储器按键驱动器来升级到更大的存储容量。 在USB双模微控制器上执行的闪存交换器程序从输入 - 输出总线复制数据，并将USB数据包生成到USB存储器键盘驱动器。