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公开(公告)号：US5245206A
公开(公告)日：1993-09-14
申请号：US881944
申请日：1992-05-12
申请人： Jack O. Chu , Louis L. Hsu , Toshio Mii , Joseph F. Shepard , Scott R. Stiffler , Manu J. Tejwani , Edward J. Vishnesky
发明人： Jack O. Chu , Louis L. Hsu , Toshio Mii , Joseph F. Shepard , Scott R. Stiffler , Manu J. Tejwani , Edward J. Vishnesky
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/94
CPC分类号： H01L28/84 , H01L29/94 , Y10S438/964
摘要： A capacitor is provided having a substrate and a first capacitor plate including a lattice mismatched crystalline material is formed over and supported by a surface of the substrate. A layer of insulating material is formed over and supported by the first capacitor plate. A second capacitor plate including a layer of conductive material is formed over and supported by the layer of insulating material.
摘要翻译： 提供一种电容器，其具有衬底，并且包括晶格失配的晶体材料的第一电容器板形成在衬底的表面上并由衬底的表面支撑。 一层绝缘材料形成在第一电容器板上并由其支撑。 包括导电材料层的第二电容器板形成在绝缘材料层的上方并由其支撑。
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公开(公告)号：US07186625B2
公开(公告)日：2007-03-06
申请号：US10709768
申请日：2004-05-27
IPC分类号： H01L21/20
CPC分类号： H01L28/91 , H01L23/5223 , H01L23/5227 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： A structure, apparatus and method for utilizing vertically interdigitated electrodes serves to increase the capacitor area surface while maintaining a minimal horizontal foot print. Since capacitance is proportional to the surface area the structure enables continual use of current dielectric materials such as Si3N4 at current thicknesses. In a second embodiment of the interdigitated MIMCAP structure the electrodes are formed in a spiral fashion which serves to increase the physical strength of the MIMCAP. Also included is a spiral shaped capacitor electrode which lends itself to modular design by offering a wide range of discrete capacitive values easily specified by the circuit designer.
摘要翻译： 用于利用垂直交错电极的结构，装置和方法用于增加电容器面积，同时保持最小的水平脚印。 由于电容与表面积成比例，因此该结构能够连续使用当前厚度的当前介电材料，例如Si 3 N 4。 在叉指MIMCAP结构的第二实施例中，电极以螺旋方式形成，其用于增加MIMCAP的物理强度。 还包括螺旋形电容器电极，其通过提供电路设计者容易指定的宽范围的离散电容值来适应模块化设计。
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公开(公告)号：US07029951B2
公开(公告)日：2006-04-18
申请号：US10661299
申请日：2003-09-12
CPC分类号： H01L23/473 , H01L21/4871 , H01L23/3677 , H01L25/0655 , H01L2224/05001 , H01L2224/05008 , H01L2224/05548 , H01L2224/16225 , H01L2924/00014 , H01L2924/01019 , H01L2924/01079 , H01L2924/10158 , H01L2924/15311 , H01L2224/05599 , H01L2224/05099
摘要： A cooling system for a semiconductor substrate incudes a plurality of trenches formed from a backside of the semiconductor substrate, and thermally conductive material deposited in the plurality of trenches. A method of forming cooling elements in a semiconductor substrate, includes coating a backside of the semiconductor substrate with a first mask layer, forming a plurality of trench patterns in the first mask layer, etching the semiconductor substrate to form a plurality of trenches along the plurality of trench patterns, and depositing thermally conductive material in the plurality of trenches. Trenches constructed from the backside of a wafer improve efficiency of heat transfer from a front-side to the backside of an integrated-circuit chip. The fabrication of trenches from the backside of the wafer allows for increases in the depth and number of trenches, and provides a means to attach passive and active cooling devices directly to the backside of a wafer.
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公开(公告)号：US06509612B2
公开(公告)日：2003-01-21
申请号：US09848431
申请日：2001-05-04
IPC分类号： H01L2976
CPC分类号： H01L21/28176 , H01L21/26506 , H01L21/26586 , H01L21/28194 , H01L29/512 , H01L29/517
摘要： A method and structure for a metal oxide semiconductor field effect transistor (MOSFET) includes patterning a gate stack (having a gate conductor layer and a gate dielectric) over a substrate and modifying the gate dielectric beneath the gate conductor, such that the gate dielectric has a central portion and modified dielectric regions adjacent the central portion. The modified dielectric regions have a lower dielectric constant than that of the gate dielectric and the central portion is shorter than the gate conductor.
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15.发明授权公开(公告)号：US06441421B1
公开(公告)日：2002-08-27
申请号：US09858485
申请日：2001-05-17
IPC分类号： H01L27108
CPC分类号： H01L27/1085 , H01L27/10861 , H01L27/10867 , H01L27/10873 , H01L27/1203 , H01L28/55
摘要： A method and structure for simultaneously producing a dynamic random access memory device and associated transistor is disclosed. The method forms channel regions and capacitor openings in a substrate. Next, the invention deposits capacitor conductors in the capacitor openings. Then, the invention simultaneously forms a single insulator layer above the channel region and above the capacitor conductor. This single insulator layer comprises a capacitor node dielectric above the capacitor conductor and comprises a gate dielectric above the channel region.
摘要翻译： 公开了一种用于同时产生动态随机存取存储器件和相关晶体管的方法和结构。 该方法在衬底中形成通道区域和电容器开口。 接下来，本发明在电容器开口中沉积电容器导体。 然后，本发明同时在沟道区域上方和电容器导体之上形成单个绝缘体层。 该单个绝缘体层包括在电容器导体上方的电容器节点电介质，并且在沟道区域上方包括栅极电介质。
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16.发明授权公开(公告)号：US07170164B2
公开(公告)日：2007-01-30
申请号：US11317298
申请日：2005-12-23
IPC分类号： H01L23/12
CPC分类号： H01L23/473 , H01L21/4871 , H01L23/3677 , H01L25/0655 , H01L2224/05001 , H01L2224/05008 , H01L2224/05548 , H01L2224/16225 , H01L2924/00014 , H01L2924/01019 , H01L2924/01079 , H01L2924/10158 , H01L2924/15311 , H01L2224/05599 , H01L2224/05099
摘要： A cooling system for a semiconductor substrate incudes a plurality of trenches formed from a backside of the semiconductor substrate, and thermally conductive material deposited in the plurality of trenches. A method of forming cooling elements in a semiconductor substrate, includes coating a backside of the semiconductor substrate with a first mask layer, forming a plurality of trench patterns in the first mask layer, etching the semiconductor substrate to form a plurality of trenches along the plurality of trench patterns, and depositing thermally conductive material in the plurality of trenches. Trenches constructed from the backside of a wafer improve efficiency of heat transfer from a front-side to the backside of an integrated-circuit chip. The fabrication of trenches from the backside of the wafer allows for increases in the depth and number of trenches, and provides a means to attach passive and active cooling devices directly to the backside of a wafer.
摘要翻译： 用于半导体衬底的冷却系统包括由半导体衬底的背面形成的多个沟槽和沉积在多个沟槽中的导热材料。 一种在半导体衬底中形成冷却元件的方法，包括用第一掩模层涂覆半导体衬底的背面，在第一掩模层中形成多个沟槽图案，蚀刻半导体衬底以形成沿着多个的多个沟槽 的沟槽图案，并且在多个沟槽中沉积导热材料。 从晶片背面构成的沟槽提高了从集成电路芯片的正面到背面的传热效率。 从晶片的背面制造沟槽允许沟槽的深度和数量的增加，并且提供了将被动和主动的冷却装置直接附接到晶片的背面的手段。
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公开(公告)号：US06794721B2
公开(公告)日：2004-09-21
申请号：US10328650
申请日：2002-12-23
IPC分类号： H01L2976
CPC分类号： H01L29/4983 , H01L21/28194 , H01L21/28518 , H01L21/28568 , H01L21/3003 , H01L21/76823 , H01L21/76895 , H01L29/517 , H01L29/7833
摘要： A method and structure for a transistor device comprises forming a source, drain, and trench region in a substrate, forming a first insulator over the substrate, forming a gate electrode above the first insulator, forming a pair of insulating spacers adjoining the electrode, converting a portion of the first insulator into a metallic film, converting the metallic film into one of a silicide and a salicide film, forming an interconnect region above the trench region, forming an etch stop layer above the first insulator, the trench region, the gate electrode, and the pair of insulating spacers, forming a second insulator above the etch stop layer, and forming contacts in the second insulator. The first insulator comprises a metal oxide material, which comprises one of a HfOx and a ZrOx.
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公开(公告)号：US06652956B2
公开(公告)日：2003-11-25
申请号：US09910763
申请日：2001-07-24
申请人： Lawrence A. Clevenger , David B. Goland , Louis L. Hsu , Joseph F. Shepard, Jr. , Subhash L. Shinde
发明人： Lawrence A. Clevenger , David B. Goland , Louis L. Hsu , Joseph F. Shepard, Jr. , Subhash L. Shinde
IPC分类号： B32B300
CPC分类号： H05K3/02 , B32B2310/085 , B32B2311/04 , B32B2311/12 , B32B2311/22 , C04B2237/40 , C04B2237/403 , C04B2237/405 , G03F7/2039 , H05K1/0306 , H05K1/092 , H05K3/207 , H05K2203/0514 , Y10S430/168 , Y10T428/24926
摘要： A method and structure to form a conductive pattern on a ceramic sheet deposits a photosensitive conductive material on a carrier and exposes a pattern of x-ray energy on the material and sinters the carrier and the material to the ceramic sheet so that only the conductive pattern of the material remains on the ceramic sheet. The structure has a conductive patterned material which includes a photosensitive agent.
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19.发明授权High dielectric constant materials forming components of DRAM such as deep-trench capacitors and gate dielectric (insulators) for support circuits 失效形成DRAM的组件的高介电常数材料，例如用于支撑电路的深沟槽电容器和栅极电介质（绝缘体）公开(公告)号：US06563160B2
公开(公告)日：2003-05-13
申请号：US09924549
申请日：2001-08-09
IPC分类号： H01L2994
CPC分类号： H01L29/945 , H01L21/28194 , H01L21/31604 , H01L21/3162 , H01L27/10829 , H01L27/1087 , H01L29/517 , H01L29/66181
摘要： A method and structure for an improved DRAM (dynamic random access memory) dielectric structure, whereby a new high-k material is implemented for both the support devices used as the gate dielectric as well as the capacitor dielectric. The method forms both deep isolated trench regions used for capacitor devices, and shallow isolated trench regions for support devices. The method also forms two different insulator layers, where one insulator layer with a uniform high-k dielectric constant is used for the deep trench regions and the support regions. The other insulator layer is used in the array regions in between the shallow trench regions.
摘要翻译： 用于改进的DRAM（动态随机存取存储器）电介质结构的方法和结构，由此为用作栅极电介质的支撑器件以及电容器电介质实现新的高k材料。 该方法形成用于电容器器件的深的隔离沟槽区域和用于支持器件的浅隔离沟槽区域。 该方法还形成两个不同的绝缘体层，其中具有均匀的高k介电常数的一个绝缘体层用于深沟槽区域和支撑区域。 另一个绝缘体层用于浅沟槽区域之间的阵列区域。
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公开(公告)号：US5395786A
公开(公告)日：1995-03-07
申请号：US269852
申请日：1994-06-30
申请人： Louis L. Hsu , Sieki Ogura , Joseph F. Shepard
发明人： Louis L. Hsu , Sieki Ogura , Joseph F. Shepard
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/8242 , H01L27/108 , H01L21/70
CPC分类号： H01L27/10861
摘要： A DRAM cell of the trench capacitor type is formed by a simplified process that reduces cost and increases process latitude by forming the trench collar in a single step of expanding a shallow trench horizontally and conformally coating the collar; etching the trench to its final depth and implanting the bottom heavily and doping the walls lightly; recessing the poly liner in a non-critical step that exposes a contact area between the top of the poly and the adjacent transistor electrode.
摘要翻译： 沟槽电容器类型的DRAM单元通过简化的工艺形成，该工艺通过在使水平并且适形地涂覆套环的单个步骤中形成沟槽套圈来降低成本并增加工艺的纬度; 将沟槽蚀刻到其最终深度并且重要地注入底部并轻轻掺杂壁; 在暴露多晶硅和相邻晶体管电极的顶部之间的接触面积的非关键步骤中使多层衬垫凹陷。
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