公开(公告)号：US06184147B2

公开(公告)日：2001-02-06

申请号：US09263421

申请日：1999-03-05

申请人： Chan-Lon Yang ,  Tong-Yu Chen ,  Keh-Ching Huang

发明人： Chan-Lon Yang ,  Tong-Yu Chen ,  Keh-Ching Huang

IPC分类号： H01L21302

CPC分类号： H01L21/76897 ,  H01J37/32082 ,  H01J2237/3347 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76802

摘要： A method for forming a high aspect ration (HAR>4:1) borderless contact hole is described. The method forms a contact/via hole in the silicon oxide layer by performing an etching process with an etchant, C4F8/C2F6,/Ar/CO or C4F8/Ar/CO, on an etcher. The etcher includes a ring, a roof, a chiller and a chamber. The etchant used in the etching process is controlled under conditions including a C4F8 flow of about 10 to 20 sccm, a CO flow of about 1 to 100 sccm, and an Ar flow of about 100 to 500 sccm. The flow of C2F6 is about 0.5 to 1.5 times that of C4F8. The conditions of the etcher include a roof temperature of about 150 to 300° C., a chiller temperature of about −20 to 20° C., a wall temperature of about 150 to 400° C., a ring temperature of about 150 to 400° C., and a pressure within the chamber of about 4 to 50 mtorr. By controlling the chamber pressure and the deposition rate of the polymer molecules, a properly profiled contact hole is obtained.

摘要翻译： 描述了形成高纵横比（HAR> 4:1）无边界接触孔的方法。 该方法通过在蚀刻剂上用蚀刻剂C 4 F 8 / C 2 F 6，/ Ar / CO或C 4 F 8 / Ar / CO执行蚀刻处理来形成氧化硅层中的接触/通孔。 蚀刻器包括环，屋顶，冷却器和室。 在蚀刻工艺中使用的蚀刻剂在约10至20sccm的C 4 F 8流量，约1至100sccm的CO流量和约100至500sccm的Ar流量的条件下进行控制。 C2F6的流量约为C4F8的0.5〜1.5倍。 蚀刻器的条件包括约150至300℃的屋顶温度，约-20至20℃的冷却器温度，约150至400℃的壁温度，约150至400℃的环境温度 400℃，室内的压力为约4至50毫托。 通过控制室压力和聚合物分子的沉积速率，获得适当的异型接触孔。

公开(公告)号：US06184142B2

公开(公告)日：2001-02-06

申请号：US09302204

申请日：1999-04-26

申请人： Hsien-Ta Chung ,  Chan-Lon Yang ,  Tong-Yu Chen ,  Tri-Rung Yew

发明人： Hsien-Ta Chung ,  Chan-Lon Yang ,  Tong-Yu Chen ,  Tri-Rung Yew

IPC分类号： H01L2100

CPC分类号： H01L21/76807 ,  H01L21/31144 ,  H01L21/76802

摘要： A simplified method is disclosed for etching low k organic dielectric film. A substrate is provided with a hardmask layer and low k organic dielectric layer formed thereon in which hardmask layer is on the dielectric layer. A layer of photoresist is formed on the hardmask layer and imaged with a pattern by exposure through a dark field mask. As a key step, the pattern is transferred into the hardmask layer by dry etching and then the photoresist is stripped in-situ. Then, the interconnect is formed by using dry etching the low k organic dielectric layer using the hardmask layer as a mask, and readying it for the next semiconductor process.

摘要翻译： 公开了一种用于蚀刻低k有机介电膜的简化方法。 衬底上设置有硬掩模层和形成在其上的低k有机介电层，其中硬掩模层位于电介质层上。 在硬掩模层上形成光致抗蚀剂层，并通过暗场掩模曝光以图案成像。 作为关键步骤，通过干蚀刻将图案转移到硬掩模层中，然后原位剥离光致抗蚀剂。 然后，通过使用硬掩模层作为掩模使用干式蚀刻低k有机介电层形成互连，并将其准备用于下一个半导体工艺。

公开(公告)号：US06180532B2

公开(公告)日：2001-01-30

申请号：US09213129

申请日：1998-12-15

申请人： Chan-Lon Yang ,  Tong-Yu Chen ,  Tsu-An Lin

发明人： Chan-Lon Yang ,  Tong-Yu Chen ,  Tsu-An Lin

IPC分类号： H01L213065

CPC分类号： H01L21/76897 ,  H01L21/31116 ,  H01L21/31144

摘要： A method for forming a contact hole in a silicon oxide layer formed over a silicon nitride layer and a substrate performs an etching process with an etchant, C4F8/Ar or C4F8/C2F6/Ar, on an inductively coupled plasma etcher. The inductively coupled plasma etcher contains a chamber, a ring, and a roof. The etchant used in the etching process is controlled by conditions that include a C4F8 flow of about 10 to 20 sccm, a CO flow of less than about 100 sccm, and an Ar flow of about 50 to 500 sccm. In the meantime, the conditions of the inductively coupled plasma etcher include a roof temperature of about 150 to 300 ° C., a ring temperature of about 150 to 400 ° C., and a pressure within the chamber of about 4 to 50 mtorr. By performing a plasma etching process under the foregoing conditions, a properly profiled contact hole is obtained.

摘要翻译： 在形成在氮化硅层和基板上的氧化硅层中形成接触孔的方法在电感耦合等离子体蚀刻器上用蚀刻剂C4F8 / Ar或C4F8 / C2F6 / Ar进行蚀刻处理。 电感耦合等离子体蚀刻器包含一个室，一个环和一个屋顶。 在蚀刻工艺中使用的蚀刻剂由包括约10至20sccm的C 4 F 8流量，小于约100sccm的CO流量和约50至500sccm的Ar流量的条件控制。 同时，电感耦合等离子体蚀刻器的条件包括约150-300℃的屋顶温度，约150-400℃的环境温度和室内压力为约4-50mtorr。 通过在上述条件下进行等离子体蚀刻工艺，可以获得适当的异型接触孔。

公开(公告)号：US6147007A

公开(公告)日：2000-11-14

申请号：US330597

申请日：1999-06-11

申请人： Chan-Lon Yang ,  Wei-Che Huang ,  Tong-Yu Chen

发明人： Chan-Lon Yang ,  Wei-Che Huang ,  Tong-Yu Chen

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/00

CPC分类号： H01L21/02063 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76814

摘要： The present invention relates to a method of forming a contact hole on the semiconductor wafer. The semiconductor wafer comprises, in ascending order, a substrate, a silicon nitride layer, a silicon oxide layer, and a photo-resist layer. There is a hole in the photo-resist layer. The method comprises: (1) performing a first anisotropic etching process in a downward direction to remove the silicon oxide layer under the hole down to the surface of the silicon nitride layer to form a recess; (2) performing an in-situ plasma cleaning process to entirely remove the polymer material remaining at the bottom of the recess; (3) performing an in-situ second anisotropic etching process in a downward direction to remove the silicon nitride layer from the bottom of the recess down to the surface of the substrate to form the contact hole; (4) performing another in-situ cleaning process to entirely remove the polymer material remaining at the bottom of the contact hole.

摘要翻译： 本发明涉及在半导体晶片上形成接触孔的方法。 半导体晶片按照升序包括衬底，氮化硅层，氧化硅层和光致抗蚀剂层。 光致抗蚀剂层中有一个孔。 该方法包括：（1）沿向下的方向进行第一各向异性蚀刻处理，以将氧化硅层下面的氮化硅层的表面去除，形成凹部; （2）进行原位等离子体清洗工艺以完全除去残留在凹部底部的聚合物材料; （3）在向下的方向上进行原位第二各向异性蚀刻工艺，以将氮化硅层从凹槽的底部向下移动到衬底的表面，以形成接触孔; （4）进行另一原位清洗处理以完全除去留在接触孔底部的聚合物材料。

公开(公告)号：US08803247B2

公开(公告)日：2014-08-12

申请号：US13326429

申请日：2011-12-15

申请人： Chih-Jung Wang ,  Tong-Yu Chen

发明人： Chih-Jung Wang ,  Tong-Yu Chen

IPC分类号： H01L27/148 ,  H01L29/66 ,  H01L29/00 ,  H01L27/088 ,  H01L21/339 ,  H01L21/00 ,  H01L21/84 ,  H01L21/338 ,  H01L21/337 ,  H01L21/336 ,  H01L21/8234

CPC分类号： H01L27/1211 ,  H01L21/845

摘要： A fin-type field effect transistor including at least one fin-type semiconductor structure, a gate strip and a gate insulating layer is provided. The fin-type semiconductor structure is doped with a first type dopant and has a block region with a first doping concentration and a channel region with a second doping concentration. The first doping concentration is larger than the second doping concentration. The blocking region has a height. The channel region is configured above the blocking region. The gate strip is substantially perpendicular to the fin-type semiconductor structure and covers above the channel region. The gate insulating layer is disposed between the gate strip and the fin-type semiconductor structure.

摘要翻译： 提供了包括至少一个鳍式半导体结构，栅极条和栅极绝缘层的鳍式场效应晶体管。 翅片型半导体结构掺杂有第一种掺杂剂并具有具有第一掺杂浓度的阻挡区和具有第二掺杂浓度的沟道区。 第一掺杂浓度大于第二掺杂浓度。 阻挡区域具有高度。 通道区域被配置在阻塞区域之上。 栅极条基本上垂直于鳍状半导体结构并且覆盖在沟道区域上方。 栅极绝缘层设置在栅极条和鳍状半导体结构之间。

公开(公告)号：US07319074B2

公开(公告)日：2008-01-15

申请号：US11160178

申请日：2005-06-13

申请人： Pei-Yu Chou ,  Tong-Yu Chen

发明人： Pei-Yu Chou ,  Tong-Yu Chen

IPC分类号： H01L21/302

CPC分类号： H01L21/32139 ,  H01L21/31138 ,  H01L21/32137

摘要： The present invention provides a method of defining polysilicon patterns. The method forms a polysilicon layer on a substrate, and a patterned mask on the polysilicon layer. Then, a first etching process is performed to remove a portion of the polysilicon layer not covered by the mask, thus forming a plurality of cavities in the polysilicon layer. A strip process is performed to strip the mask utilizing gases excluding O2. Finally, a second etching process is performed to remove a portion of the polysilicon layer, thus extending the plurality of cavities down to a surface of the substrate.

摘要翻译： 本发明提供了一种限定多晶硅图案的方法。 该方法在衬底上形成多晶硅层，并在多晶硅层上形成图案化掩模。 然后，进行第一蚀刻处理以去除未被掩模覆盖的多晶硅层的一部分，从而在多晶硅层中形成多个空腔。 执行条带处理以利用除O 2以外的气体剥离掩模。 最后，执行第二蚀刻工艺以去除多晶硅层的一部分，从而将多个空腔向下延伸到衬底的表面。

公开(公告)号：US06972259B2

公开(公告)日：2005-12-06

申请号：US10291911

申请日：2002-11-13

申请人： Chih-Jung Wang ,  Tong-Yu Chen

发明人： Chih-Jung Wang ,  Tong-Yu Chen

IPC分类号： H01L21/027 ,  H01L21/28 ,  H01L21/302 ,  H01L21/311 ,  H01L21/4763 ,  H01L21/768 ,  H01L29/40

CPC分类号： H01L21/76811 ,  H01L21/0276 ,  H01L21/31144 ,  H01L21/76813

摘要： The invention is directed towards a method for forming openings in low-k dielectric layers and a structure for forming an opening thereof. A mask layer comprising at least one metal hard mask layer and one or more hard mask layers is applied on the dielectric layer for forming the opening.

公开(公告)号：US09105590B2

公开(公告)日：2015-08-11

申请号：US13206523

申请日：2011-08-10

申请人： Tong-Yu Chen

发明人： Tong-Yu Chen

IPC分类号： H01L29/06 ,  H01L21/3213 ,  H01L21/033 ,  H01L21/768

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/76816 ,  H01L21/76838

摘要： A semiconductor structure is provided in the present invention. The semiconductor structure includes a substrate, a first material layer and a second material layer. A trench region is defined on the substrate. The trench region includes two separated first regions and a second region, wherein the second region is adjacent to and between the two first regions. The first material layer is disposed on the substrate outside the trench region. The second material layer is disposed in the second region and is level with the first material layer.

摘要翻译： 在本发明中提供半导体结构。 半导体结构包括基板，第一材料层和第二材料层。 在衬底上限定沟槽区域。 沟槽区域包括两个分开的第一区域和第二区域，其中第二区域与两个第一区域相邻并且在两个第一区域之间。 第一材料层设置在沟槽区域外的衬底上。 第二材料层设置在第二区域中并与第一材料层平齐。

公开(公告)号：US09012975B2

公开(公告)日：2015-04-21

申请号：US13517759

申请日：2012-06-14

申请人： Tong-Yu Chen ,  Chih-Jung Wang

发明人： Tong-Yu Chen ,  Chih-Jung Wang

IPC分类号： H01L29/792 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L29/423

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/42344 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/792

摘要： A field effect transistor (FET) and a manufacturing method thereof are provided. The FET includes a substrate, a fin bump, an insulating layer, a charge trapping structure and a gate structure. The fin bump is disposed on the substrate. The insulating layer is disposed on the substrate and located at two sides of the fin bump. The charge trapping structure is disposed on the insulating layer and located at at least one side of the fin bump. A cross-section of the charge trapping structure is L-shaped. The gate structure covers the fin bump and the charge trapping structure.

摘要翻译： 提供场效应晶体管（FET）及其制造方法。 FET包括衬底，鳍片凸块，绝缘层，电荷俘获结构和栅极结构。 翅片凸块设置在基板上。 绝缘层设置在基板上并且位于散热片凸块的两侧。 电荷捕获结构设置在绝缘层上并位于散热片凸块的至少一侧。 电荷捕获结构的横截面为L形。 栅极结构覆盖鳍片凸起和电荷俘获结构。

公开(公告)号：US08946078B2

公开(公告)日：2015-02-03

申请号：US13426624

申请日：2012-03-22

申请人： Tong-Yu Chen ,  Chih-Jung Wang

发明人： Tong-Yu Chen ,  Chih-Jung Wang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76807 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28132 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/311 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/31144 ,  H01L29/66795

摘要： The present invention provides a method of forming a trench in a semiconductor substrate. First, a first patterned mask layer is formed on a semiconductor substrate. The first patterned mask layer has a first trench. Then, a material layer is formed along the first trench. Then, a second patterned mask layer is formed on the material layer to completely fill the first trench. A part of the material layer is removed when the portion of the material layer between the second patterned mask layer and the semiconductor substrate is maintained so as to form a second trench. Lastly, an etching process is performed by using the first patterned mask layer and the second patterned mask layer as a mask.

摘要翻译： 本发明提供一种在半导体衬底中形成沟槽的方法。 首先，在半导体衬底上形成第一图案化掩模层。 第一图案化掩模层具有第一沟槽。 然后，沿着第一沟槽形成材料层。 然后，在材料层上形成第二图案化掩模层以完全填充第一沟槽。 当保持第二图案化掩模层和半导体衬底之间的材料层的部分以形成第二沟槽时，去除材料层的一部分。 最后，通过使用第一图案化掩模层和第二图案化掩模层作为掩模来执行蚀刻工艺。