公开(公告)号：US08921978B2

公开(公告)日：2014-12-30

申请号：US13347031

申请日：2012-01-10

申请人： Chi-Feng Huang ,  Chia-Chung Chen ,  Victor Chiang Liang ,  Hsiao-Chun Lee

发明人： Chi-Feng Huang ,  Chia-Chung Chen ,  Victor Chiang Liang ,  Hsiao-Chun Lee

IPC分类号： H01L21/70

CPC分类号： H01L21/823892 ,  H01L21/761 ,  H01L27/0928

摘要： An isolation structure in a semiconductor device absorbs electronic noise and prevents substrate leakage currents from reaching other devices and signals. The isolation structure provides a duality of deep N-well (“DNW”) isolation structures surrounding an RF device or other source of electronic noise. The DNW isolation structures extend into the substrate at a depth of at least about 2.5 μm and may be coupled to VDD. P+ guard rings are also provided in some embodiments and are provided inside, outside or between the dual DNW isolation structures.

摘要翻译： 半导体器件中的隔离结构吸收电子噪声并防止衬底漏电流到达其它器件和信号。 隔离结构提供了围绕RF器件或其他电子噪声源的深N阱（“DNW”）隔离结构的二元性。 DNW隔离结构在至少约2.5μm的深度延伸到衬底中，并且可以耦合到VDD。 在一些实施例中还提供了P +保护环，并且设置在双DNW隔离结构内部，外部或之间。

公开(公告)号：US20140001518A1

公开(公告)日：2014-01-02

申请号：US13539027

申请日：2012-06-29

申请人： Chi-Feng Huang ,  Chia-Chung Chen ,  Victor Chiang Liang ,  Mingo Liu

发明人： Chi-Feng Huang ,  Chia-Chung Chen ,  Victor Chiang Liang ,  Mingo Liu

IPC分类号： H01L27/07 ,  H01L21/8249

CPC分类号： H01L21/8249 ,  H01L27/0623 ,  H01L27/07 ,  H01L27/085 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/732 ,  H01L29/7327 ,  H01L29/808 ,  H01L29/861 ,  H01L29/93

摘要： A method includes forming a deep well region of a first conductivity type in a substrate, implanting a portion of the deep well region to form a first gate, and implanting the deep well region to form a well region. The well region and the first gate are of a second conductivity type opposite the first conductivity type. An implantation is performed to form a channel region of the first conductivity type over the first gate. A portion of the deep well region overlying the channel region is implanted to form a second gate of the second conductivity type. A source/drain implantation is performed to form a source region and a drain region of the first conductivity type on opposite sides of the second gate. The source and drain regions are connected to the channel region, and overlap the channel region and the first gate.

摘要翻译： 一种方法包括在衬底中形成第一导电类型的深阱区域，注入深阱区域的一部分以形成第一栅极，以及植入深阱区域以形成阱区域。 阱区和第一栅极是与第一导电类型相反的第二导电类型。 执行注入以在第一栅极上形成第一导电类型的沟道区。 植入覆盖沟道区域的深阱区域的一部分以形成第二导电类型的第二栅极。 进行源极/漏极注入以在第二栅极的相对侧上形成第一导电类型的源极区域和漏极区域。 源极和漏极区域连接到沟道区域，并且与沟道区域和第一栅极重叠。

公开(公告)号：US20120104387A1

公开(公告)日：2012-05-03

申请号：US12915757

申请日：2010-10-29

申请人： Chia-Chung Chen ,  Chi-Feng Huang ,  Tse-Hua Lu ,  Sally Liu

发明人： Chia-Chung Chen ,  Chi-Feng Huang ,  Tse-Hua Lu ,  Sally Liu

IPC分类号： H01L23/544 ,  H01L29/92

CPC分类号： H01L23/5223 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A device includes a first MOM capacitor; a second MOM capacitor directly over and vertically overlapping the first MOM capacitor, wherein each of the first and the second MOM capacitors includes a plurality of parallel capacitor fingers; a first and a second port electrically coupled to the first MOM capacitor; and a third and a fourth port electrically coupled to the second MOM capacitor. The first, the second, the third, and the fourth ports are disposed at a surface of a respective wafer.

摘要翻译： 一种器件包括第一MOM电容器; 第二MOM电容器直接在第一MOM电容器上方并垂直重叠，其中第一和第二MOM电容器中的每一个包括多个并联电容指; 电耦合到第一MOM电容器的第一和第二端口; 以及电耦合到第二MOM电容器的第三和第四端口。 第一，第二，第三和第四端口设置在相应晶片的表面。

公开(公告)号：US20100323237A1

公开(公告)日：2010-12-23

申请号：US12486386

申请日：2009-06-17

申请人： Chi-Feng Huang ,  Jen-Chu Hsu ,  Chih-Tsung Hu ,  Chung Jen Ho ,  Hao-Ming Chen

发明人： Chi-Feng Huang ,  Jen-Chu Hsu ,  Chih-Tsung Hu ,  Chung Jen Ho ,  Hao-Ming Chen

IPC分类号： H01M2/00

CPC分类号： H01R13/6315 ,  H01M2/20

摘要： An information handling system (IHS) includes an IHS chassis having a processor and defining a battery housing. An IHS connector is located adjacent the battery housing and is electrically coupled to the processor. A battery is located in the battery housing and includes a battery chassis that houses at least one battery cell. A battery connector is electrically coupled to the at least one battery cell and engages the IHS connector. The battery connector is moveably coupled to the battery chassis through a battery connector coupling that allows the battery connector to move relative to the battery chassis when the battery connector engages the IHS connector.

摘要翻译： 信息处理系统（IHS）包括具有处理器并且限定电池外壳的IHS底盘。 IHS连接器位于电池壳体附近并且电耦合到处理器。 电池位于电池壳体中，并且包括容纳至少一个电池单体的电池底盘。 电池连接器电耦合到至少一个电池单元并且接合IHS连接器。 电池连接器通过电池连接器可移动地联接到电池盒，当电池连接器接合IHS连接器时，电池连接器可以相对于电池盒移动。

公开(公告)号：US07757923B2

公开(公告)日：2010-07-20

申请号：US12219353

申请日：2008-07-21

申请人： Chi-Feng Huang ,  I-Hui Liu ,  Chun-Hsien Chiang

发明人： Chi-Feng Huang ,  I-Hui Liu ,  Chun-Hsien Chiang

IPC分类号： B25C5/11 ,  B25C5/02

CPC分类号： B25C5/0207 ,  B25C5/0242

摘要： A stapler has a supporting base, a magazine assembly, a trigger assembly and a leg-flatting device. The trigger assembly has a trigger lever and a pushing element. The pushing element is mounted pivotally on the trigger lever with a pivot and has two pushing arms extending toward the supporting base. The leg-flatting device is mounted on the supporting base and has a sliding base, a moving base and an anvil element. The sliding base is slidably mounted on the supporting base and has a pushed segment corresponding to and selectively pushed by the pushing arms. The moving base is selectively blocked by the sliding base to keep the moving base from moving downwardly before the sliding base sliding relative to the supporting base and has an elongated hole. The anvil element is mounted in the elongated hole in the moving base.

公开(公告)号：US07122878B2

公开(公告)日：2006-10-17

申请号：US11143229

申请日：2005-06-02

申请人： Chi-Feng Huang ,  Chun-Hon Chen ,  Shy Chy Wong ,  Chih Hsien Lin

发明人： Chi-Feng Huang ,  Chun-Hon Chen ,  Shy Chy Wong ,  Chih Hsien Lin

IPC分类号： H01L29/00

CPC分类号： H01L28/60 ,  H01L21/28568 ,  H01L21/3143 ,  H01L21/31608 ,  H01L21/31637 ,  H01L21/3185 ,  H01L21/76838 ,  H01L28/75

摘要： A new method is provided for the creation of a high-reliability metal capacitor as part of back-end processing. A first layer of metal interconnect is created, ac contact point is provided in the surface of the first layer of interconnect aligned with which a capacitor is to be created. A copper interconnect is formed overlying the contact point using TaN for the bottom plate, a high dielectric-constant dielectric material capacitor and using TaN for the top plate. The deposited layers are patterned and etched, a spacer layer is formed over sidewalls of the capacitor to prevent capacitor sidewall leakage. Top interconnect metal is then formed by first depositing a layer of etch stop material for further interconnection of the capacitor and the semiconductor devices provided in the underlying substrate.

摘要翻译： 提供了一种用于创建高可靠性金属电容器作为后端处理的一部分的新方法。 产生金属互连的第一层，在要与其形成电容器的第一互连层的表面上提供交流接触点。 使用用于底板的TaN，高介电常数介电材料电容器和使用TaN作为顶板，形成覆盖接触点的铜互连。 沉积的层被图案化和蚀刻，在电容器的侧壁上形成间隔层以防止电容器侧壁泄漏。 然后通过首先沉积一层蚀刻停止材料形成顶部互连金属，用于电容器和设置在下面的衬底中的半导体器件的进一步互连。

公开(公告)号：US06916722B2

公开(公告)日：2005-07-12

申请号：US10307617

申请日：2002-12-02

申请人： Chi-Feng Huang ,  Chun-Hon Chen ,  Shy-Chy Wong ,  Chih Hsien Lin

发明人： Chi-Feng Huang ,  Chun-Hon Chen ,  Shy-Chy Wong ,  Chih Hsien Lin

IPC分类号： H01L21/02 ,  H01L21/285 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L21/20

CPC分类号： H01L28/60 ,  H01L21/28568 ,  H01L21/3143 ,  H01L21/31608 ,  H01L21/31637 ,  H01L21/3185 ,  H01L21/76838 ,  H01L28/75

摘要： A new method is provided for the creation of a high-reliability metal capacitor as part of back-end processing. A first layer of metal interconnect is created, a contact point is provided in the surface of the first layer of interconnect aligned with which a capacitor is to be created. A copper interconnect is formed overlying the contact point using TaN for the bottom plate, a high dielectric-constant dielectric material capacitor and using TaN for the top plate. The deposited layers are patterned and etched, a spacer layer is formed over sidewalls of the capacitor to prevent capacitor sidewall leakage. Top interconnect metal is then formed by first depositing a layer of etch stop material for further interconnection of the capacitor and the semiconductor devices provided in the underlying substrate.

摘要翻译： 提供了一种用于创建高可靠性金属电容器作为后端处理的一部分的新方法。 产生第一层金属互连，在第一层互连层的表面上提供一个接触点，与其形成电容器。 使用用于底板的TaN，高介电常数介电材料电容器和使用TaN作为顶板，形成覆盖接触点的铜互连。 沉积的层被图案化和蚀刻，在电容器的侧壁上形成间隔层以防止电容器侧壁泄漏。 然后通过首先沉积一层蚀刻停止材料形成顶部互连金属，以便电容器和设置在下面的衬底中的半导体器件进一步互连。

公开(公告)号：US09209098B2

公开(公告)日：2015-12-08

申请号：US13111730

申请日：2011-05-19

申请人： Chia-Chung Chen ,  Chi-Feng Huang ,  Tse-Hua Lu

发明人： Chia-Chung Chen ,  Chi-Feng Huang ,  Tse-Hua Lu

IPC分类号： G01R27/08 ,  H01L21/66 ,  G01R31/02 ,  H01L29/78 ,  H01L29/10

CPC分类号： H01L27/092 ,  G01R27/08 ,  G01R31/02 ,  H01L22/14 ,  H01L22/34 ,  H01L27/0207 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/1087 ,  H01L29/7835

摘要： A method of determining the reliability of a high-voltage PMOS (HVPMOS) device includes determining a bulk resistance of the HVPMOS device, and evaluating the reliability of the HVPMOS device based on the bulk resistance.

摘要翻译： 确定高压PMOS（HVPMOS）器件的可靠性的方法包括确定HVPMOS器件的体电阻，以及基于体电阻来评估HVPMOS器件的可靠性。

公开(公告)号：US20140042506A1

公开(公告)日：2014-02-13

申请号：US13570157

申请日：2012-08-08

申请人： Fredrik Ramberg ,  Tse-Hua Lu ,  Tsun-Lai Hsu ,  Victor Chiang Liang ,  Chi-Feng Huang ,  Yu-Lin Wei ,  Shu Fang Fu

发明人： Fredrik Ramberg ,  Tse-Hua Lu ,  Tsun-Lai Hsu ,  Victor Chiang Liang ,  Chi-Feng Huang ,  Yu-Lin Wei ,  Shu Fang Fu

IPC分类号： H01L29/78 ,  H01L31/08 ,  H01L21/336

CPC分类号： H01L27/14614 ,  H01L27/14616 ,  H01L29/0653 ,  H01L29/4238 ,  H01L29/7838

摘要： Transistors, methods of manufacturing thereof, and image sensor circuits are disclosed. In one embodiment, a transistor includes a buried channel disposed in a workpiece, a gate dielectric disposed over the buried channel, and a gate layer disposed over the gate dielectric. The gate layer comprises an I shape in a top view of the transistor.

摘要翻译： 公开了晶体管，其制造方法和图像传感器电路。 在一个实施例中，晶体管包括设置在工件中的掩埋沟道，设置在掩埋沟道上方的栅极电介质和设置在栅极电介质上的栅极层。 栅极层在晶体管的俯视图中包括I形状。

公开(公告)号：US08388115B2

公开(公告)日：2013-03-05

申请号：US13218917

申请日：2011-08-26

申请人： Chiang-Ho Cheng ,  Chi-Feng Huang

发明人： Chiang-Ho Cheng ,  Chi-Feng Huang

IPC分类号： B41J2/045

CPC分类号： B41J2/14209 ,  B41J2/1609 ,  B41J2/1623 ,  B41J2/1632 ,  B41J2002/14491

摘要： A piezoelectric inkjet head structure includes an upper cover plate, a lower cover plate, a piezoelectric actuating module, a nozzle plate and a seal layer. The piezoelectric actuating module includes an upper piezoelectric chip, a lower piezoelectric chip, a first electrode, a second electrode, a conductive layer and a plurality of flow channels. The entrances of the flow channels of the upper piezoelectric chip and the lower piezoelectric chip are separated from each other by the same spacing interval. The entrances of the flow channels of the upper piezoelectric chip and the entrances of the flow channels of the lower piezoelectric chip are arranged in a staggered form. During operation of the piezoelectric actuating module, ink liquid is introduced into the flow channels of the piezoelectric actuating module from the upper cover plate and the lower cover plate, and then ejected out of the nozzles.

摘要翻译： 压电喷墨头结构包括上盖板，下盖板，压电致动模块，喷嘴板和密封层。 压电致动模块包括上压电芯片，下压电芯片，第一电极，第二电极，导电层和多个流动通道。 上压电芯片和下压电芯片的流动通道的入口以相同的间隔间隔彼此分开。 上压电芯片的流路的通道和下压电芯片的流道的入口以交错的形式布置。 在压电致动模块的操作期间，油墨从上盖板和下盖板引入压电致动模块的流动通道中，然后从喷嘴中排出。