公开(公告)号：US20110107006A1

公开(公告)日：2011-05-05

申请号：US12929222

申请日：2011-01-10

申请人： Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Ho-Cheol Lee ,  Soo-Young Kim ,  Dong-Hyuk Lee ,  Chang-Ho Lee

发明人： Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Ho-Cheol Lee ,  Soo-Young Kim ,  Dong-Hyuk Lee ,  Chang-Ho Lee

IPC分类号： G06F12/00

CPC分类号： G06F12/02

摘要： A multiprocessor system and method thereof are provided. The example multiprocessor system may include first and second processors, a dynamic random access memory having a memory cell array, the memory cell array including a first memory bank coupled to the first processor through a first port, second and fourth memory banks coupled to the second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports, and a bank address assigning unit for assigning bank addresses to select individually the first and second memory banks, as the same bank address through the first and second ports, so that starting addresses for the first and second memory banks become equal in booting, and assigning bank addresses to select the third memory bank, as different bank addresses through the first and second ports, and assigning, through the second port, bank addresses to select the fourth memory bank, as the same bank address as a bank address to select the third memory bank through the first port.

公开(公告)号：US20080172516A1

公开(公告)日：2008-07-17

申请号：US11819601

申请日：2007-06-28

申请人： Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Ho-Cheol Lee ,  Soo-Young Kim ,  Dong-Hyuk Lee ,  Chang-Ho Lee

发明人： Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Ho-Cheol Lee ,  Soo-Young Kim ,  Dong-Hyuk Lee ,  Chang-Ho Lee

IPC分类号： G06F12/02

CPC分类号： G06F12/02

摘要： A multiprocessor system and method thereof are provided. The example multiprocessor system may include first and second processors, a dynamic random access memory having a memory cell array, the memory cell array including a first memory bank coupled to the first processor through a first port, second and fourth memory banks coupled to the second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports, and a bank address assigning unit for assigning bank addresses to select individually the first and second memory banks, as the same bank address through the first and second ports, so that starting addresses for the first and second memory banks become equal in booting, and assigning bank addresses to select the third memory bank, as different bank addresses through the first and second ports, and assigning, through the second port, bank addresses to select the fourth memory bank, as the same bank address as a bank address to select the third memory bank through the first port.

摘要翻译： 提供了一种多处理器系统及其方法。 示例性多处理器系统可以包括第一和第二处理器，具有存储单元阵列的动态随机存取存储器，所述存储单元阵列包括通过第一端口耦合到第一处理器的第一存储器组，耦合到第二存储器组的第二存储器组和第四存储器组 处理器通过第二端口和通过第一和第二端口与第一和第二处理器共享并连接的第三存储器组，以及用于分配存储体地址以选择单独地选择第一和第二存储体的存储体地址分配单元，如同样的 通过第一和第二端口的存储器地址，使得第一和第二存储器组的起始地址在引导中变得相等，并且通过第一和第二端口分配存储体地址以选择第三存储体作为不同的存储体地址， 通过第二个端口，银行地址选择第四个存储器，作为银行地址作为银行地址，选择第三个存储器 银行通过第一个港口。

公开(公告)号：US20100322021A1

公开(公告)日：2010-12-23

申请号：US12788029

申请日：2010-05-26

申请人： Ho-Young Kim ,  Ho-Cheol Lee ,  Jung-Bae Lee

发明人： Ho-Young Kim ,  Ho-Cheol Lee ,  Jung-Bae Lee

IPC分类号： G11C7/00 ,  G11C8/18

CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/222 ,  G11C2207/2272

摘要： A semiconductor memory device is disclosed. The semiconductor device includes a memory cell array, a clock signal generator configured to receive an external clock signal from the outside of the memory device and output an internal clock signal, and a data output unit configured to receive an internal data signal from the memory cell array and output a read data signal in response to the internal clock signal. The semiconductor memory device also includes a read data strobe unit configured to output a read data strobe signal having a cycle time of n times (n is an integer equal to or more than 2) a cycle time of the internal clock signal, based on the internal clock signal.

摘要翻译： 公开了一种半导体存储器件。 半导体器件包括存储单元阵列，时钟信号发生器，被配置为从存储器件的外部接收外部时钟信号并输出​​内部时钟信号;以及数据输出单元，被配置为从存储器单元接收内部数据信号 阵列并响应于内部时钟信号输出读取数据信号。 半导体存储器件还包括读取数据选通单元，其被配置为基于内部时钟信号的周期时间，输出具有n倍（n是等于或大于2的整数）的周期时间的读取数据选通信号 内部时钟信号。

公开(公告)号：US20120188834A1

公开(公告)日：2012-07-26

申请号：US13441713

申请日：2012-04-06

申请人： Ho-Young Kim ,  Ho-Cheol Lee ,  Jung-Bae Lee

发明人： Ho-Young Kim ,  Ho-Cheol Lee ,  Jung-Bae Lee

IPC分类号： G11C7/22

CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/222 ,  G11C2207/2272

摘要： A semiconductor memory device is disclosed. The semiconductor device includes a memory cell array, a clock signal generator configured to receive an external clock signal from the outside of the memory device and output an internal clock signal, and a data output unit configured to receive an internal data signal from the memory cell array and output a read data signal in response to the internal clock signal. The semiconductor memory device also includes a read data strobe unit configured to output a read data strobe signal having a cycle time of n times (n is an integer equal to or more than 2) a cycle time of the internal clock signal, based on the internal clock signal.

摘要翻译： 公开了一种半导体存储器件。 半导体器件包括存储单元阵列，时钟信号发生器，被配置为从存储器件的外部接收外部时钟信号并输出​​内部时钟信号;以及数据输出单元，被配置为从存储器单元接收内部数据信号 阵列并响应于内部时钟信号输出读取数据信号。 半导体存储器件还包括读取数据选通单元，其被配置为基于内部时钟信号的周期时间，输出具有n倍（n是等于或大于2的整数）的周期时间的读取数据选通信号 内部时钟信号。

公开(公告)号：US08391095B2

公开(公告)日：2013-03-05

申请号：US12768060

申请日：2010-04-27

申请人： Ho-Cheol Lee ,  Jung-Bae Lee

发明人： Ho-Cheol Lee ,  Jung-Bae Lee

IPC分类号： G11C5/14

CPC分类号： G11C5/148 ,  G11C5/144 ,  G11C5/147 ,  G11C8/16

摘要： Disclosed is a method of controlling a deep power down mode in a multi-port semiconductor memory having a plurality of ports connected to a plurality of processors. Control of the deep power down mode in the multi-port semiconductor memory is performed such that activation/deactivation of the deep power down mode are determined in accordance with signals applied through various ports in the plurality of ports.

摘要翻译： 公开了一种在多端口半导体存储器中控制深度掉电模式的方法，该多端口半导体存储器具有连接到多个处理器的多个端口。 执行多端口半导体存储器中的深度掉电模式的控制，使得根据通过多个端口中的各个端口施加的信号来确定深度掉电模式的激活/去激活。

公开(公告)号：US08154934B2

公开(公告)日：2012-04-10

申请号：US12788029

申请日：2010-05-26

申请人： Ho-Young Kim ,  Ho-Cheol Lee ,  Jung-Bae Lee

发明人： Ho-Young Kim ,  Ho-Cheol Lee ,  Jung-Bae Lee

IPC分类号： G11C7/00 ,  G11C8/18

CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/222 ,  G11C2207/2272

摘要： A semiconductor memory device is disclosed. The semiconductor device includes a memory cell array, a clock signal generator configured to receive an external clock signal from the outside of the memory device and output an internal clock signal, and a data output unit configured to receive an internal data signal from the memory cell array and output a read data signal in response to the internal clock signal. The semiconductor memory device also includes a read data strobe unit configured to output a read data strobe signal having a cycle time of n times (n is an integer equal to or more than 2) a cycle time of the internal clock signal, based on the internal clock signal.

摘要翻译： 公开了一种半导体存储器件。 半导体器件包括存储单元阵列，时钟信号发生器，被配置为从存储器件的外部接收外部时钟信号并输出​​内部时钟信号;以及数据输出单元，被配置为从存储器单元接收内部数据信号 阵列并响应于内部时钟信号输出读取数据信号。 半导体存储器件还包括读取数据选通单元，其被配置为基于内部时钟信号的周期时间，输出具有n倍（n是等于或大于2的整数）的周期时间的读取数据选通信号 内部时钟信号。

公开(公告)号：US08625381B2

公开(公告)日：2014-01-07

申请号：US13026460

申请日：2011-02-14

申请人： Ho-Cheol Lee

发明人： Ho-Cheol Lee

IPC分类号： G11C5/06 ,  G11C5/02 ,  H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/00 ,  G11C8/02 ,  G11C8/12 ,  G11C8/10

CPC分类号： H01L23/544 ,  H01L24/04 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/18 ,  H01L2223/54433 ,  H01L2223/5444 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/01055 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/05552

摘要： Provided is a stacked semiconductor device including n stacked chips. Each chip includes “j” corresponding upper and lower electrodes, wherein j is a minimal natural number greater than or equal to n/2, and an identification code generator including a single inverter connecting one of the j first upper electrode to a corresponding one of the j lower electrodes. The upper electrodes receive a previous identification code, rotate the previous identification code by a unit of 1 bit, and invert 1 bit of the rotated previous identification code to generate a current identification code. The current identification code is applied through the j lower electrodes and corresponding TSVs to communicate the current identification code to the upper adjacent chip.

摘要翻译： 提供了包括n个堆叠芯片的堆叠半导体器件。 每个芯片包括对应的上部和下部电极的“j”，其中j是大于或等于n / 2的最小自然数，以及识别码发生器，其包括将j个第一上电极中的一个连接到 j个下电极。 上电极接收先前的识别码，以1位为单位旋转先前的识别码，并且反转已转动的先前识别码的1位，以产生当前识别码。 通过j个下部电极和相应的TSV施加当前的识别码，以将当前识别码传送到上部相邻的芯片。

公开(公告)号：US20080205175A1

公开(公告)日：2008-08-28

申请号：US12068280

申请日：2008-02-05

申请人： Sang-Kyun Park ,  Ho-Cheol Lee

发明人： Sang-Kyun Park ,  Ho-Cheol Lee

IPC分类号： G11C7/00

CPC分类号： G11C11/4076 ,  G11C7/1072 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4094 ,  G11C2207/229

摘要： An auto-precharge control circuit in a semiconductor memory and method thereof, where the auto-precharge starting point may vary. The auto-precharge starting point may vary in response to at least one control signal. The auto-precharge starting point may vary in accordance with frequency and/or latency information. The auto-precharge starting point may vary in response to at least one control signal including clock frequency information. The auto-precharge starting point may vary depending on a latency signal received from a mode register setting command. The auto-precharge control circuit may include a control circuit for receiving a write signal, a clock signal and at least one control signal, including at least one of clock frequency information and latency information, and outputting at least one path signal; an auto-precharge pulse signal driver for receiving the at least one path signal, the write signal, and an enable signal and producing an auto-precharge pulse signal, the auto-precharge pulse signal identifying a starting point for an auto-precharge operation; and an auto-precharge mode enabling circuit for receiving the clock signal, an auto-precharge command, an active signal, and the auto-precharge pulse signal and generating the enable signal.

摘要翻译： 半导体存储器中的自动预充电控制电路及其方法，其中自动预充电起点可以变化。 自动预充电起始点可以响应于至少一个控制信号而变化。 自动预充电起始点可以根据频率和/或延迟信息而变化。 响应于包括时钟频率信息的至少一个控制信号，自动预充电起始点可以变化。 自动预充电起点可以根据从模式寄存器设置命令接收到的等待时间信号而变化。 自动预充电控制电路可以包括用于接收包括时钟频率信息和等待时间信息中的至少一个的写入信号，时钟信号和至少一个控制信号的控制电路，并且输出至少一个路径信号; 自动预充电脉冲信号驱动器，用于接收至少一个路径信号，写入信号和使能信号，并产生自动预充电脉冲信号，所述自动预充电脉冲信号标识自动预充电操作的起始点; 以及自动预充电模式使能电路，用于接收时钟信号，自动预充电命令，有效信号和自动预充电脉冲信号，并产生使能信号。

公开(公告)号：US06928023B2

公开(公告)日：2005-08-09

申请号：US10465553

申请日：2003-06-20

申请人： Ho-Cheol Lee ,  Jung-Soo Ryoo

发明人： Ho-Cheol Lee ,  Jung-Soo Ryoo

IPC分类号： G11C7/00 ,  G11C5/06 ,  G11C5/14 ,  G11C8/12

CPC分类号： G11C5/063 ,  G11C5/14 ,  G11C8/12

摘要： A method of controlling a bank voltage (AIVC) through memory block selection information, said method comprising the steps of detecting an array block selection signal of an array block disposed distantly from an AIVC driver in response to an activated memory array block selection signal; and supplying a second bank voltage to a memory bank by driving a normal size driver and an oversize driver when detecting the array block selection signal for the distantly disposed array block.

摘要翻译： 一种通过存储块选择信息控制存储体电压（AIVC）的方法，所述方法包括以下步骤：响应激活的存储器阵列块选择信号，检测远离AIVC驱动器的阵列块的阵列块选择信号; 以及当检测到用于远处布置的阵列块的阵列块选择信号时，通过驱动正常尺寸的驱动器和超大驱动器，将第二存储体电压提供给存储体。

公开(公告)号：US5631871A

公开(公告)日：1997-05-20

申请号：US578151

申请日：1995-12-29

申请人： Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

发明人： Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

IPC分类号： G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/409 ,  B01F7/00 ,  B01F13/00

CPC分类号： G11C7/1018 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4082 ,  G11C11/4087 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/222 ,  G11C7/225 ,  G11C2207/2281

摘要： A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

摘要翻译： 能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。 同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路 响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到 当锁存的逻辑电平为第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的失活信号，使得响应于激活信号的所选择的存储器组在活动周期中工作，而未选定的存储器组响应于 灭活信号在预充电循环中工作。