公开(公告)号：US08802524B2

公开(公告)日：2014-08-12

申请号：US13053223

申请日：2011-03-22

Applicant: Po-Jui Liao ,  Tsung-Lung Tsai ,  Chien-Ting Lin ,  Shao-Hua Hsu ,  Yi-Wei Chen ,  Hsin-Fu Huang ,  Tzung-Ying Lee ,  Min-Chuan Tsai ,  Chan-Lon Yang ,  Chun-Yuan Wu ,  Teng-Chun Tsai ,  Guang-Yaw Hwang ,  Chia-Lin Hsu ,  Jie-Ning Yang ,  Cheng-Guo Chen ,  Jung-Tsung Tseng ,  Zhi-Cheng Lee ,  Hung-Ling Shih ,  Po-Cheng Huang ,  Yi-Wen Chen ,  Che-Hua Hsu

Inventor： Po-Jui Liao ,  Tsung-Lung Tsai ,  Chien-Ting Lin ,  Shao-Hua Hsu ,  Yi-Wei Chen ,  Hsin-Fu Huang ,  Tzung-Ying Lee ,  Min-Chuan Tsai ,  Chan-Lon Yang ,  Chun-Yuan Wu ,  Teng-Chun Tsai ,  Guang-Yaw Hwang ,  Chia-Lin Hsu ,  Jie-Ning Yang ,  Cheng-Guo Chen ,  Jung-Tsung Tseng ,  Zhi-Cheng Lee ,  Hung-Ling Shih ,  Po-Cheng Huang ,  Yi-Wen Chen ,  Che-Hua Hsu

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823842 ,  H01L21/823807 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7833

Abstract: The present invention provides a method of manufacturing semiconductor device having metal gates. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench. Then, a first metal layer is formed in the first trench. The second sacrifice gate is removed to form a second trench. Next, a second metal layer is formed in the first trench and the second trench. Lastly, a third metal layer is formed on the second metal layer wherein the third metal layer is filled into the first trench and the second trench.

Abstract translation: 本发明提供一种制造具有金属栅极的半导体器件的方法。 首先，提供基板。 具有第一牺牲栅极的第一导电型晶体管和具有第二牺牲栅极的第二导电型晶体管设置在衬底上。 去除第一牺牲栅极以形成第一沟槽。 然后，在第一沟槽中形成第一金属层。 去除第二牺牲栅极以形成第二沟槽。 接下来，在第一沟槽和第二沟槽中形成第二金属层。 最后，在第二金属层上形成第三金属层，其中第三金属层被填充到第一沟槽和第二沟槽中。

公开(公告)号：US08709910B2

公开(公告)日：2014-04-29

申请号：US13459262

申请日：2012-04-30

Applicant: Chin-I Liao ,  Chia-Lin Hsu ,  Yung-Lun Hsieh ,  Chien-Hao Chen ,  Bo-Syuan Lee ,  Min-Chung Cheng

Inventor： Chin-I Liao ,  Chia-Lin Hsu ,  Yung-Lun Hsieh ,  Chien-Hao Chen ,  Bo-Syuan Lee ,  Min-Chung Cheng

IPC: H01L21/76

CPC classification number: H01L21/0237 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/76224 ,  H01L29/66795

Abstract: A semiconductor process includes the following steps. A semiconductor substrate is provided. The semiconductor substrate has a patterned isolation layer and the patterned isolation layer has an opening exposing a silicon area of the semiconductor substrate. A silicon rich layer is formed on the sidewalls of the opening. An epitaxial process is performed to form an epitaxial structure on the silicon area in the opening.

Abstract translation: 半导体工艺包括以下步骤。 提供半导体衬底。 半导体衬底具有图案化隔离层，并且图案化隔离层具有暴露半导体衬底的硅区域的开口。 在开口的侧壁上形成富硅层。 执行外延工艺以在开口中的硅区域上形成外延结构。

公开(公告)号：US08643069B2

公开(公告)日：2014-02-04

申请号：US13180556

申请日：2011-07-12

Applicant: Chun-Wei Hsu ,  Po-Cheng Huang ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Chih-Hsun Lin ,  Yen-Ming Chen ,  Chia-Hsi Chen ,  Chang-Hung Kung

Inventor： Chun-Wei Hsu ,  Po-Cheng Huang ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Chih-Hsun Lin ,  Yen-Ming Chen ,  Chia-Hsi Chen ,  Chang-Hung Kung

IPC: H01L29/76 ,  H01L21/02

CPC classification number: H01L21/28008 ,  H01L21/28123 ,  H01L21/31053 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

Abstract: A semiconductor device having a metal gate includes a substrate having a plurality of shallow trench isolations (STIs) formed therein, at least a metal gate positioned on the substrate, and at least a pair of auxiliary dummy structures respectively positioned at two sides of the metal gate and on the substrate.

Abstract translation: 具有金属栅极的半导体器件包括具有形成在其中的至少一个金属栅极的多个浅沟槽隔离物（STI）的基板，以及分别位于金属的两侧的至少一对辅助虚设结构 门和衬底上。

公开(公告)号：US20130341638A1

公开(公告)日：2013-12-26

申请号：US13530127

申请日：2012-06-22

Applicant: Chin-I Liao ,  Chia-Lin Hsu ,  Ming-Yen Li ,  Yung-Lun Hsieh ,  Chien-Hao Chen ,  Bo-Syuan Lee

Inventor： Chin-I Liao ,  Chia-Lin Hsu ,  Ming-Yen Li ,  Yung-Lun Hsieh ,  Chien-Hao Chen ,  Bo-Syuan Lee

IPC: H01L29/772 ,  H01L21/20 ,  H01L29/161

CPC classification number: H01L29/66795 ,  H01L29/1054 ,  H01L29/66484 ,  H01L29/785

Abstract: A Multi-Gate Field-Effect Transistor includes a fin-shaped structure, a gate structure, at least an epitaxial structure and a gradient cap layer. The fin-shaped structure is located on a substrate. The gate structure is disposed across a part of the fin-shaped structure and the substrate. The epitaxial structure is located on the fin-shaped structure beside the gate structure. The gradient cap layer is located on each of the epitaxial structures. The gradient cap layer is a compound semiconductor, and the concentration of one of the ingredients of the compound semiconductor has a gradient distribution decreasing from bottom to top. Moreover, the present invention also provides a Multi-Gate Field-Effect Transistor process forming said Multi-Gate Field-Effect Transistor.

Abstract translation: 多栅极场效应晶体管包括鳍状结构，栅极结构，至少外延结构和梯度盖层。 鳍状结构位于基板上。 栅极结构设置在鳍状结构和衬底的一部分上。 外延结构位于栅极结构旁边的鳍状结构上。 梯度盖层位于每个外延结构上。 梯度盖层是化合物半导体，化合物半导体的成分之一的浓度具有从下到上减小的梯度分布。 此外，本发明还提供一种形成所述多栅极场效应晶体管的多栅极场效应晶体管工艺。

公开(公告)号：US20130105912A1

公开(公告)日：2013-05-02

申请号：US13283603

申请日：2011-10-28

Applicant: Chun-Wei Hsu ,  Po-Cheng Huang ,  Ren-Peng Huang ,  Jie-Ning Yang ,  Chia-Lin Hsu ,  Teng-Chun Tsai ,  Chih-Hsun Lin ,  Chang-Hung Kung ,  Yen-Ming Chen ,  Yu-Ting Li

Inventor： Chun-Wei Hsu ,  Po-Cheng Huang ,  Ren-Peng Huang ,  Jie-Ning Yang ,  Chia-Lin Hsu ,  Teng-Chun Tsai ,  Chih-Hsun Lin ,  Chang-Hung Kung ,  Yen-Ming Chen ,  Yu-Ting Li

IPC: H01L27/06 ,  H01L21/8234

CPC classification number: H01L27/0629

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation (STI) on the substrate of the resistor region; forming a tank in the STI of the resistor region; and forming a resistor in the tank and on the surface of the STI adjacent to two sides of the tank.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供具有晶体管区域和电阻器区域的衬底; 在电阻器区域的衬底上形成浅沟槽隔离（STI）; 在电阻区域的STI中形成槽; 并且在罐中形成电阻器，并且在与槽的两侧相邻的STI的表面上形成电阻器。

公开(公告)号：US20130052778A1

公开(公告)日：2013-02-28

申请号：US13216259

申请日：2011-08-24

Applicant: Chin-I Liao ,  Chia-Lin Hsu ,  Ming-Yen Li ,  Hsin-Huei Wu ,  Yung-Lun Hsieh ,  Chien-Hao Chen ,  Bo-Syuan Lee

Inventor： Chin-I Liao ,  Chia-Lin Hsu ,  Ming-Yen Li ,  Hsin-Huei Wu ,  Yung-Lun Hsieh ,  Chien-Hao Chen ,  Bo-Syuan Lee

IPC: H01L21/336

CPC classification number: H01L29/66795 ,  H01L29/66628

Abstract: A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate. An oxide layer is formed on the substrate without the fin-shaped structure being formed thereon. A gate is formed to cover a part of the oxide layer and a part of the fin-shaped structure. An etching process is performed to etch a part of the fin-shaped structure beside the gate, therefore at least a recess is formed in the fin-shaped structure. An epitaxial process is performed to form an epitaxial layer in the recess, wherein the epitaxial layer has a hexagon-shaped profile structure.

Abstract translation: 半导体工艺包括以下步骤。 提供基板。 在基板上形成至少一个鳍状结构。 在基板上形成氧化层，而不形成鳍状结构。 形成栅极以覆盖氧化物层的一部分和鳍状结构的一部分。 进行蚀刻处理以蚀刻栅极旁边的鳍状结构的一部分，因此在鳍状结构中至少形成凹部。 执行外延工艺以在凹部中形成外延层，其中外延层具有六边形轮廓结构。

公开(公告)号：US20130015524A1

公开(公告)日：2013-01-17

申请号：US13180556

申请日：2011-07-12

Applicant: Chun-Wei Hsu ,  Po-Cheng Huang ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Chih-Hsun Lin ,  Yen-Ming Chen ,  Chia-Hsi Chen ,  Chang-Hung Kung

Inventor： Chun-Wei Hsu ,  Po-Cheng Huang ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Chih-Hsun Lin ,  Yen-Ming Chen ,  Chia-Hsi Chen ,  Chang-Hung Kung

IPC: H01L29/78 ,  H01L21/28

CPC classification number: H01L21/28008 ,  H01L21/28123 ,  H01L21/31053 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

Abstract: A semiconductor device having a metal gate includes a substrate having a plurality of shallow trench isolations (STIs) formed therein, at least a metal gate positioned on the substrate, and at least a pair of auxiliary dummy structures respectively positioned at two sides of the metal gate and on the substrate.

Abstract translation: 具有金属栅极的半导体器件包括具有形成在其中的至少一个金属栅极的至少一个金属栅极和分别位于该金属的两侧的至少一对辅助虚拟结构的基板，其中形成有多个浅沟槽隔离物（STI） 门和衬底上。

公开(公告)号：US07368042B2

公开(公告)日：2008-05-06

申请号：US10905361

申请日：2004-12-30

Applicant: Chia-Lin Hsu ,  Kun-Hsien Lin ,  Wen-Chieh Su

Inventor： Chia-Lin Hsu ,  Kun-Hsien Lin ,  Wen-Chieh Su

IPC: B23H3/02

CPC classification number: C25D17/001 ,  C25D17/12 ,  C25D21/12

Abstract: An electro-chemical plating system includes an upper rotor assembly for receiving and holding a wafer; an electroplating reactor vessel for containing plating solution in which the wafer is immersed; an anode array including a plurality of concentric anode segments provided inside the electroplating reactor vessel; a power supply system including power supply subunits for controlling electrical potentials of the anode segments, respectively; and a plurality of sensor devices mounted inside the upper rotor assembly, wherein the sensor devices are substantially arranged in corresponding to the anode segments, and during operation, the plurality of sensor devices are utilized for in-situ feeding back a deposition profile to a control unit in real time.

Abstract translation: 电化学电镀系统包括用于接收和保持晶片的上转子组件; 电镀反应器容器，用于容纳浸有晶片的镀液; 阳极阵列，包括设置在所述电镀反应器容器内部的多个同心阳极段; 电源系统，包括分别用于控制阳极段的电位的电源子单元; 以及安装在上转子组件内部的多个传感器装置，其中传感器装置基本上布置成对应于阳极段，并且在操作期间，多个传感器装置用于将沉积轮廓原位反馈到控制器 单位实时。

公开(公告)号：US20070056024A1

公开(公告)日：2007-03-08

申请号：US11162276

申请日：2005-09-05

Applicant: Ho-Hsiung Hsu ,  Chia-Lin Hsu

Inventor： Ho-Hsiung Hsu ,  Chia-Lin Hsu

IPC: H04L9/32

CPC classification number: H04L63/083

Abstract: A method for remote server login is disclosed, in which the method using a second pathway for remote server login is adopted. When a user requires to login to the remote server, he receives a virtual account by entering a user account. The virtual account and a password are then entered into the remote server using another device. After the remote server successfully authenticates the virtual account and the password, the user is authorized by the remote server to login. As a result, the objective for providing secure user login for remote server is achieved.

Abstract translation: 公开了一种用于远程服务器登录的方法，其中采用了用于远程服务器登录的第二路径的方法。 当用户需要登录到远程服务器时，他通过输入用户帐号来接收虚拟帐户。 然后，使用其他设备将虚拟帐户和密码输入到远程服务器。 远程服务器成功验证虚拟帐号和密码后，远程服务器授权用户登录。 因此，实现了为远程服务器提供安全用户登录的目的。

公开(公告)号：US20060172526A1

公开(公告)日：2006-08-03

申请号：US11331361

申请日：2006-01-13

Applicant: Chia-Lin Hsu ,  Shu-Hsien Lee ,  Chien-Chien Tsai ,  Hsiao-Ling Lu

Inventor： Chia-Lin Hsu ,  Shu-Hsien Lee ,  Chien-Chien Tsai ,  Hsiao-Ling Lu

IPC: H01L21/4763

CPC classification number: H01L21/0209 ,  H01L21/02087 ,  H01L21/76883

Abstract: A method for improving edge peeling defect is disclosed in this invention. According to this invention, a wafer can be kept from the edge peeling defect of the prior art by introducing a step for removing the weakly adhesive films and the metal structures at the wafer edge after forming a metal interconnect layer on the wafer. Thus, this invention can raise the yield of semiconductor manufacturing, and reduce the pollution chance of the chamber of the semiconductor manufacture.

Abstract translation: 本发明公开了一种改善边缘剥离缺陷的方法。 根据本发明，通过在晶片上形成金属互连层之后，通过引入在晶片边缘处去除弱粘合膜和金属结构的步骤，可以保持晶片免受现有技术的边缘剥离缺陷的影响。 因此，本发明可以提高半导体制造的产量，并且减少半导体制造室的污染机会。