利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

58 条记录 (耗时 0.021 秒)

    Method for planarization of wafers with high selectivities
    15.
    发明授权
    Method for planarization of wafers with high selectivities 有权
    具有高选择性的晶片平面化方法

    公开(公告)号：US06660627B2

    公开(公告)日：2003-12-09

    申请号：US10063133

    申请日：2002-03-25

    申请人： Shao-Chung Hu ,  Hsueh-Chung Chen ,  Shih-Hsun Hsu ,  Chia-Lin Hsu

    发明人： Shao-Chung Hu ,  Hsueh-Chung Chen ,  Shih-Hsun Hsu ,  Chia-Lin Hsu

    IPC分类号： H01L214763

    CPC分类号： H01L21/7684 ,  H01L21/31051

    摘要： A method for planarization of a semiconductor wafer with a high selectivity is describe. The semiconductor wafer has a hard mask, a stop layer disposed on the hard mask, and a barrier layer disposed on the stop layer. The method includes performing a chemical mechanical polishing (CMP) process on the barrier layer so as to expose the stop layer, and removing the stop layer. The polishing selectivity of the barrier layer relative to the stop layer is greater than 50. Since the material of stop layer is different from the material of barrier layer, the high selectivity is easily achieved. Thus, the surface of semiconductor wafer can be highly planarized.

    摘要翻译： 描述了一种以高选择性平坦化半导体晶片的方法。 半导体晶片具有硬掩模，设置在硬掩模上的阻挡层和设置在阻挡层上的阻挡层。 该方法包括在阻挡层上进行化学机械抛光（CMP）处理，以露出停止层，并除去停止层。 阻挡层相对于停止层的抛光选择性大于50.由于阻挡层的材料与阻挡层的材料不同，因此容易实现高选择性。 因此，半导体晶片的表面可以被高度平坦化。

    CHEMICAL MECHANICAL POLISHING PROCESS
    17.
    发明申请
    CHEMICAL MECHANICAL POLISHING PROCESS 审中-公开
    化学机械抛光工艺

    公开(公告)号：US20060057945A1

    公开(公告)日：2006-03-16

    申请号：US10904251

    申请日：2004-11-01

    申请人： Chia-Lin Hsu ,  Teng-Chun Tsai

    发明人： Chia-Lin Hsu ,  Teng-Chun Tsai

    IPC分类号： B24B1/00

    CPC分类号： C09G1/02 ,  B24B37/042 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76843

    摘要： A first substrate and second substrate both having thereon a top bulk metal layer and a lower barrier layer are prepared. The first substrate is first loaded onto a first platen of a CMP tool, and then an upper portion of the top bulk metal layer of the first substrate is removed by first platen and first slurry. The first substrate is then transferred to a second platen having second slurry. The second substrate is loaded onto the first platen. Simultaneously, the remaining top bulk metal layer of the first substrate and an upper portion of top bulk metal layer of the second substrate are removed at substantially the same copper removal rate until the lower barrier layer of the first substrate is exposed. The first substrate is transferred to a third platen having third slurry for polishing the exposed barrier layer.

    摘要翻译： 制备其上具有顶部本体金属层和下部阻挡层的第一基板和第二基板。 首先将第一衬底装载到CMP工具的第一压板上，然后通过第一压板和第一浆料除去第一衬底的顶部本体金属层的上部。 然后将第一衬底转移到具有第二浆料的第二压板。 将第二基板装载到第一压板上。 同时，以基本相同的铜去除速率除去第一基板的剩余顶部本体金属层和第二基板的顶部本体金属层的上部，直到暴露第一​​基板的下部阻挡层。 将第一衬底转移到具有第三浆料的第三压板上，用于抛光暴露的阻挡层。

    Semiconductor process
    18.
    发明授权
    Semiconductor process 有权
    半导体工艺

    公开(公告)号：US08647986B2

    公开(公告)日：2014-02-11

    申请号：US13220692

    申请日：2011-08-30

    申请人： Po-Cheng Huang ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Chun-Wei Hsu ,  Yen-Ming Chen ,  Chih-Hsun Lin ,  Chang-Hung Kung

    发明人： Po-Cheng Huang ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Chun-Wei Hsu ,  Yen-Ming Chen ,  Chih-Hsun Lin ,  Chang-Hung Kung

    IPC分类号： H01L21/306 ,  H01L21/321 ,  H01L21/3105 ,  H01L21/768

    CPC分类号： H01L21/3212 ,  H01L21/3105 ,  H01L21/31051 ,  H01L21/31053 ,  H01L21/7684 ,  H01L21/823835 ,  H01L29/665

    摘要： A semiconductor process includes the following steps. A first gate structure and a second gate structure are formed on a substrate, wherein the top of the first gate structure includes a cap layer, so that the vertical height of the first gate structure is higher than the vertical height of the second gate structure. An interdielectric layer is formed on the substrate. A first chemical mechanical polishing process is performed to expose the top surface of the cap layer. A second chemical mechanical polishing process is performed to expose the top surface of the second gate structure or an etching process is performed to remove the interdielectric layer located on the second gate structure. A second chemical mechanical polishing process is then performed to remove the cap layer.

    摘要翻译： 半导体工艺包括以下步骤。 第一栅极结构和第二栅极结构形成在基板上，其中第一栅极结构的顶部包括盖层，使得第一栅极结构的垂直高度高于第二栅极结构的垂直高度。 在基板上形成介电层。 执行第一化学机械抛光工艺以暴露盖层的顶表面。 执行第二化学机械抛光工艺以暴露第二栅极结构的顶表面，或执行蚀刻工艺以去除位于第二栅极结构上的介电层。 然后执行第二化学机械抛光工艺以除去盖层。

    METHOD FOR CLEANING SURFACE CONTAINING Cu
    20.
    发明申请
    METHOD FOR CLEANING SURFACE CONTAINING Cu 审中-公开
    清洗含Cu表面的方法

    公开(公告)号：US20110189855A1

    公开(公告)日：2011-08-04

    申请号：US12699071

    申请日：2010-02-03

    申请人： Jen-Chieh Lin ,  Kai-Chun Yang ,  Chih-Yueh Li ,  Geng-Yu Fan ,  Jeng-Yu Fang ,  Teng-Chun Tsai ,  Chia-Lin Hsu

    发明人： Jen-Chieh Lin ,  Kai-Chun Yang ,  Chih-Yueh Li ,  Geng-Yu Fan ,  Jeng-Yu Fang ,  Teng-Chun Tsai ,  Chia-Lin Hsu

    IPC分类号： H01L21/306

    CPC分类号： H01L21/306

    摘要： A method for cleaning a surface is disclosed. First, a substrate including Cu and a barrier layer is provided. Second, a first chemical mechanical polishing procedure is performed on the substrate. Then, a second chemical mechanical polishing procedure is performed on the barrier layer. The second chemical mechanical polishing procedure includes performing a main chemical mechanical polishing procedure to partially remove the barrier layer and performing a chemical buffing procedure on the substrate using a chemical solution which has a pH value of about 6 to about 8 to remove residues on the substrate after the main chemical mechanical polishing procedure. Later, a water rinsing procedure is performed on the substrate. Afterwards, a post clean procedure is performed on the substrate after the second chemical mechanical polishing procedure.

    摘要翻译： 公开了一种清洁表面的方法。 首先，提供包含Cu和阻挡层的基板。 其次，在基板上进行第一化学机械抛光工序。 然后，在阻挡层上进行第二化学机械抛光工序。 第二化学机械抛光方法包括执行主要的化学机械抛光方法以部分去除阻挡层并使用pH值为约6至约8的化学溶液在基底上进行化学抛光过程以去除基底上的残留物 经过主要的化学机械抛光程序。 之后，在基板上进行水洗工序。 之后，在第二化学机械抛光程序之后，在基板上执行后清洁程序。