公开(公告)号：US07804382B2

公开(公告)日：2010-09-28

申请号：US12048481

申请日：2008-03-14

申请人： Jea-Shik Shin ,  Yun-Kwon Park ,  In-Sang Song ,  Duck-Hwan Kim ,  Chul-Soo Kim

发明人： Jea-Shik Shin ,  Yun-Kwon Park ,  In-Sang Song ,  Duck-Hwan Kim ,  Chul-Soo Kim

IPC分类号： H03H9/13 ,  H03H9/15 ,  H03H9/54 ,  H03H3/04

CPC分类号： H03H9/171 ,  H03H2009/02173

摘要： A tunable resonator is provided. The tunable resonator includes a film bulk acoustic resonator (FBAR) for performing a resonance, and at least one driver which is arranged at a side of the FBAR and is deformed and brought into contact with the FBAR by an external signal, thereby changing a resonance frequency of the FBAR. Accordingly, a multiband integration and a one-chip manufacture can be implemented simply using a micro electro mechanical system (MEMS) technology and a mass production is possible.

摘要翻译： 提供可调谐谐振器。 可调谐谐振器包括用于进行谐振的膜体声波谐振器（FBAR）和至少一个驱动器，该驱动器布置在FBAR的一侧并通过外部信号变形并与FBAR接触，从而改变谐振 FBAR的频率。 因此，可以简单地使用微机电系统（MEMS）技术来实现多频带集成和单芯片制造，并且可以批量生产。

公开(公告)号：US20050253631A1

公开(公告)日：2005-11-17

申请号：US11126428

申请日：2005-05-10

申请人： Chul-Soo Kim ,  Byung-Hoon Jeong

发明人： Chul-Soo Kim ,  Byung-Hoon Jeong

IPC分类号： G11C8/00 ,  G11C7/10 ,  H03L7/00 ,  H03L7/081

CPC分类号： H03L7/0812 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/222

摘要： We describe and claim an internal signal replication device and method. A circuit comprising a selector to select one of a plurality of internally generated clock signals, and a compensation circuit to replicate the selected clock signal from a reference clock signal.

摘要翻译： 我们描述并要求内部信号复制设备和方法。 一种电路，包括选择器以选择多个内部产生的时钟信号中的一个，以及补偿电路，以从参考时钟信号复制所选择的时钟信号。

公开(公告)号：US06603687B2

公开(公告)日：2003-08-05

申请号：US10074592

申请日：2002-02-11

申请人： Young-Hyun Jun ,  Chul-Soo Kim ,  Ho-Young Song

发明人： Young-Hyun Jun ,  Chul-Soo Kim ,  Ho-Young Song

IPC分类号： G11C700

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/222

摘要： Devices, circuits and methods synchronize the inputting and outputting of groups of data into a memory cell array and out of a device. Synchronizing is performed by internal clock signals, both of which are derived from a single delay feedback loop.

摘要翻译： 设备，电路和方法将数据组的输入和输出同步到存储单元阵列中并从设备中输出。 通过内部时钟信号执行同步，两者都是从单个延迟反馈回路得出的。

公开(公告)号：US5812464A

公开(公告)日：1998-09-22

申请号：US748196

申请日：1996-11-12

申请人： Chul-Soo Kim

发明人： Chul-Soo Kim

IPC分类号： G11C11/413 ,  G11C7/22 ,  G11C11/407 ,  G11C7/00

CPC分类号： G11C7/22

摘要： Column select circuits and methods for read/write memory devices logically combine and delay an enable signal and a read/write control signal, to produce a column select control signal which has a first enable interval during a read operation and a second enable interval during a write operation. The first enable interval is preferably shorter than the second enable interval. The column select control signal preferably ends at the same time for both the read and write operations, but begins at different times for the read and write operations. Accordingly, the enable interval for the control signal can be different during read and write operations, to allow sufficient time for each of these operations while increasing access speed and preventing errors.

摘要翻译： 用于读/写存储器件的列选择电路和方法逻辑组合并延迟使能信号和读/写控制信号，以产生列选择控制信号，其在读操作期间具有第一使能间隔，在第 写操作。 第一使能间隔优选地小于第二使能间隔。 列选择控制信号优选在读和写操作两者同时结束，但是对于读和写操作在不同的时间开始。 因此，在读取和写入操作期间，控制信号的使能间隔可以是不同的，以允许这些操作中的每一个的足够的时间，同时增加访问速度并防止错误。

公开(公告)号：US5699299A

公开(公告)日：1997-12-16

申请号：US590707

申请日：1995-12-05

申请人： Chul-Soo Kim

发明人： Chul-Soo Kim

IPC分类号： G11C11/41 ,  G11C8/10 ,  G11C8/12 ,  G11C11/401 ,  G11C11/407 ,  G11C13/00

CPC分类号： G11C8/12 ,  G11C8/10

摘要： A semiconductor memory device with a plurality of column select lines and a column driving method therefore are disclosed. In a semiconductor memory device including memory blocks each having a plurality of column lines and including a column decoder for receiving a plurality of column predecoding signals and selecting the column lines, the column lines contained in each of the memory blocks are divided into a plurality of column groups. Divided column predecoding lines for selecting the column lines contained in the column groups are arranged in a corresponding memory block, and the divided column predecoding line groups adjacently extend over any one side of the corresponding memory block.

摘要翻译： 因此，公开了具有多个列选择线和列驱动方法的半导体存储器件。 在包括具有多列列的存储块的半导体存储器件中，包括用于接收多个列预解码信号并选择列线的列解码器，每个存储块中包含的列线被分成多个 列组。 用于选择列组中包含的列线的分割列预解码线被布置在相应的存储块中，并且分割的列预解码线组在对应的存储块的任一侧相邻延伸。

公开(公告)号：US07998834B2

公开(公告)日：2011-08-16

申请号：US12646691

申请日：2009-12-23

申请人： Chul-Soo Kim ,  Kuk-Jin Chun ,  Sung-Chan Kang ,  Jong-Hyuk Kim ,  In-Sang Song ,  Duck-Hwan Kim ,  Jae-Shik Shin

发明人： Chul-Soo Kim ,  Kuk-Jin Chun ,  Sung-Chan Kang ,  Jong-Hyuk Kim ,  In-Sang Song ,  Duck-Hwan Kim ,  Jae-Shik Shin

IPC分类号： H01L21/30 ,  H01L21/00

CPC分类号： H01L23/10 ,  H01L21/50 ,  H01L21/76898 ,  H01L25/50 ,  H01L27/14601 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed are a substrate level bonding method and a substrate level package formed thereby. The substrate level package includes a plurality of unit substrate sections, a base substrate, and a plurality of substrate adhesion sections. The unit substrate sections are separated from each other by holes. The base substrate is disposed to face the unit substrate sections. The substrate adhesion sections are interposed between the unit substrate sections and the base substrate to bond the unit substrate sections to the base substrate and which are formed of DFR material, whose at least one portion is uncured.

摘要翻译： 公开了一种由此形成的衬底水平焊接方法和衬底层封装。 基板级封装包括多个单元基板部分，基底基板和多个基板粘合部分。 单元基板部分通过孔彼此分离。 基底基板设置成面对单元基板部分。 基板粘合部分插入在单元基板部分和基底基板之间，以将单元基板部分粘合到基底基板上，并且由至少一部分未固化的DFR材料形成。

公开(公告)号：US07855926B2

公开(公告)日：2010-12-21

申请号：US11188184

申请日：2005-07-20

申请人： Sang-Woong Shin ,  Chul-Soo Kim ,  Young-Hyun Jun ,  Sang-Bo Lee

发明人： Sang-Woong Shin ,  Chul-Soo Kim ,  Young-Hyun Jun ,  Sang-Bo Lee

IPC分类号： G11C7/00 ,  G11C7/02

CPC分类号： G11C7/06 ,  G11C11/4091 ,  G11C2207/005 ,  G11C2207/065

摘要： A semiconductor memory device includes a plurality of memory cell array blocks, a bit line sense amplifier, a local sense amplifier that can be controlled to be turned on or off, a data sense amplifier, and a controller. The controller activates a local sense control signal for a predetermined duration in response to first and second signals. The first signal is a bit line sense enable signal that activates the bit line sense amplifier, and the local sense amplifier is activated for a predetermined duration after the bit line sense enable signal is activated. The second signal is activated or deactivated in phase with a column selection line signal that connects a pair of bit lines and a pair of local input/output lines. Accordingly, it is possible to turn on or off the local sense amplifier according to operating conditions, thereby increasing a tRCD parameter and reducing the consumption of current. The operating speed of the semiconductor memory device can be improved by combining the local sense amplifier with a current type data sense amplifier that does not require precharging and equalization during a read operation.

摘要翻译： 半导体存储器件包括多个存储单元阵列块，位线读出放大器，可被控制为导通或截止的本地读出放大器，数据读出放大器和控制器。 控制器响应于第一和第二信号激活预定持续时间的局部感测控制信号。 第一信号是激活位线读出放大器的位线检测使能信号，并且在位线检测使能信号被激活之后局部读出放大器被激活预定的持续时间。 第二信号与连接一对位线和一对本地输入/输出线的列选择线信号同相激活或去激活。 因此，可以根据操作条件接通或关闭本地读出放大器，由此增加tRCD参数并减少电流消耗。 可以通过组合本地读出放大器与在读取操作期间不需要预充电和均衡的电流型数据读出放大器来提高半导体存储器件的工作速度。

公开(公告)号：US07471589B2

公开(公告)日：2008-12-30

申请号：US11506878

申请日：2006-08-21

申请人： Doo-Young Kim ,  Soon-Seob Lee ,  Chul-Soo Kim

发明人： Doo-Young Kim ,  Soon-Seob Lee ,  Chul-Soo Kim

IPC分类号： G11C7/00

CPC分类号： G11C8/10

摘要： Semiconductor memory devices, block select decoding circuits and a method of activating a word line are provided. An example semiconductor memory device may include a plurality of memory banks. Each of the plurality of memory banks may include memory blocks which may be arranged in different addressable orders. If two edge memory blocks are activated in a given one of the plurality of memory banks, a non-edge memory block may be concurrently activated in at least one of remaining memory banks other than the given one memory bank. Accordingly, a number of concurrently activated memory blocks, a voltage required to enable a word line and noise may be reduced. The example semiconductor device may include the example block select decoding circuit, and likewise may perform the example method of activating a word line with an activation of a reduced number of memory blocks.

摘要翻译： 提供半导体存储器件，块选择解码电路和激活字线的方法。 示例性半导体存储器件可以包括多个存储体。 多个存储体中的每一个可以包括可以以不同的可寻址顺序排列的存储块。 如果在多个存储体中的给定的一个存储体中激活了两个边缘存储器块，则非边缘存储器块可以在除给定的一个存储体之外的剩余存储体的至少一个中同时激活。 因此，可以减少多个同时激活的存储块，使得字线和噪声所需的电压。 示例性半导体器件可以包括示例块选择解码电路，并且同样可以执行用减少数量的存储器块的激活来激活字线的示例方法。

公开(公告)号：US07366822B2

公开(公告)日：2008-04-29

申请号：US10840268

申请日：2004-05-07

申请人： Jin-Seok Kwak ,  Young-Hyun Jun ,  Seong-Jin Jang ,  Sang-Bo Lee ,  Min-Sang Park ,  Chul-Soo Kim

发明人： Jin-Seok Kwak ,  Young-Hyun Jun ,  Seong-Jin Jang ,  Sang-Bo Lee ,  Min-Sang Park ,  Chul-Soo Kim

IPC分类号： G06F12/00 ,  G11C8/00

CPC分类号： G11C7/1066 ,  G11C7/1072 ,  G11C11/4082 ,  G11C11/4087

摘要： A semiconductor memory device includes a plurality of banks. A data path may be divided into a read data path and a write data path, therefore, parallel processing of write and read commands are possible. The semiconductor memory device may include an address bank buffer, address buffer, column predecoder and/or a decoder. The semiconductor memory device may begin execution of a write command in a bank in one clock cycle and begin execution of a read command in the following clock cycle, therefore, bus efficiency is increased and/or write-to-read turn around time is reduced.

摘要翻译： 半导体存储器件包括多个存储体。 数据路径可以被划分为读取数据路径和写入数据路径，因此并行处理写入和读取命令是可能的。 半导体存储器件可以包括地址库缓冲器，地址缓冲器，列预解码器和/或解码器。 半导体存储器件可以在一个时钟周期内开始执行存储体中的写入命令，并且在随后的时钟周期开始执行读取命令，因此总线效率增加和/或写入读取时间减少 。

公开(公告)号：US20070061649A1

公开(公告)日：2007-03-15

申请号：US11463965

申请日：2006-08-11

申请人： Chul-Soo Kim

发明人： Chul-Soo Kim

IPC分类号： G01R31/28

CPC分类号： G01R31/31922 ,  G01R31/3016 ,  G01R31/31725

摘要： A semiconductor device may include a control signal generator configured to generate a test control signal in response to an externally applied test command signal. First and second transmission gates may be configured to open and close together in response to a test clock signal pulse and the test control signal. A delay circuit may be coupled between the first and second transmission gates so that the delay circuit is configured to receive a test input signal through the first transmission gate and to transmit a delayed test input signal to the second transmission gate, and the delayed test input signal may correspond to the test input signal. A latch may be coupled between the second transmission gate and an output of the semiconductor device, and the latch may be configured to latch a first logic value when a duration of the test clock signal pulse is less than a delay of the delay circuit and to latch a second logic value when a duration of the test clock signal pulse is greater than the delay of the delay circuit, and the first and second logic values be different. Related methods are also discussed.

摘要翻译： 半导体器件可以包括被配置为响应于外部施加的测试命令信号而产生测试控制信号的控制信号发生器。 第一和第二传输门可以被配置为响应于测试时钟信号脉冲和测试控制信号而一起打开和关闭。 延迟电路可以耦合在第一和第二传输门之间，使得延迟电路被配置为通过第一传输门接收测试输入信号，并将延迟的测试输入信号发送到第二传输门，并且延迟测试输入 信号可以对应于测试输入信号。 闩锁可以耦合在第二传输门和半导体器件的输出之间，并且锁存器可以被配置为当测试时钟信号脉冲的持续时间小于延迟电路的延迟时锁存第一逻辑值，并且 当测试时钟信号脉冲的持续时间大于延迟电路的延迟时，锁存第二逻辑值，并且第一和第二逻辑值不同。 还讨论了相关方法。