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    Pulse edge detection circuit
    11.
    发明授权
    Pulse edge detection circuit 有权

    公开(公告)号：US12135345B2

    公开(公告)日：2024-11-05

    申请号：US17942216

    申请日：2022-09-12

    Applicant: DENSO CORPORATION

    Inventor： Takasuke Ito ,  Tomohiro Nezuka ,  Yasuaki Aoki ,  Yuuta Nakamura ,  Takashi Yoshiya

    IPC: G01R29/02 ,  G01R19/165

    Abstract: In a pulse edge detection circuit, a measurement circuit has a comparator provided therein which compares a voltage with a reference voltage and outputs a pulse signal. An RSFF puts a signal in a high level at a timing at which detecting a rise edge due to a change of the pulse signal to the high level. In such manner, a set signal of an RSFF becomes inactive and a reset signal of the RSFF becomes active, and a fall edge of the pulse signal becomes detectable. When a fall edge is generated due to a change of the pulse signal from the high level to the low level, the set signal of the RSFF becomes active, and a signal becomes high level.

    Low-leak potential selection circuit
    13.
    发明授权
    Low-leak potential selection circuit 有权

    公开(公告)号：US09742401B2

    公开(公告)日：2017-08-22

    申请号：US15078013

    申请日：2016-03-23

    Applicant: DENSO CORPORATION

    Inventor： Shogo Kawahara ,  Tomohiro Nezuka

    IPC: H03K17/00 ,  H03K17/693 ,  H03M1/00

    CPC classification number: H03K17/693 ,  H03M1/00 ,  H03M3/464

    Abstract: First and second p-type transistors are connected in series between an output terminal and a positive power terminal. First and second n-type transistors are connected in series between a node and a negative power terminal. A third p-type transistor is connected between a node and the positive power terminal. Third and fourth n-type transistors are connected in series between the output terminal and a low potential terminal. Fourth and fifth p-type transistors are connected in series between a node and the negative power terminal. A fifth n-type transistor is connected between a node and the negative power terminal. A high potential is outputted without leak current when the first to fifth p-type transistors are turned on and the first to fifth n-type transistors are turned off.

    A/D conversion system
    14.
    发明授权
    A/D conversion system 有权
    A / D转换系统

    公开(公告)号：US09071259B2

    公开(公告)日：2015-06-30

    申请号：US14471418

    申请日：2014-08-28

    Applicant: DENSO CORPORATION

    Inventor： Tomohiro Nezuka

    IPC: H03M3/00 ,  H03M1/00

    CPC classification number: H03M1/001 ,  H03M3/384 ,  H03M3/422 ,  H03M3/43 ,  H03M3/438 ,  H03M3/454 ,  H03M3/46 ,  H03M3/496

    Abstract: An input signal is quantized by a quantizer after being passed through plural loop filters. A last-stage loop filter is formed of an operational amplifier for generating an output signal, a sampling capacitor for sampling the input signal, an integrating capacitor for integrating the signal sampled by the capacitor and plural switches for switching over signal paths. A control circuit controls on/off states of the switches to discharge the sampling capacitor and the integrating capacitor and causes the loop filter to repeat a sampling operation and an integrating operation plural times. The control circuit lastly connects the sampling capacitor and the integrating capacitor to a state, which is opposite to the state of the integrating operation time and turns on a converting switch so that the A/D converter A/D-converts the output signal of the loop filter.

    Abstract translation: 在通过多个环路滤波器之后，由量化器对输入信号进行量化。 最后一级环路滤波器由用于产生输出信号的运算放大器，用于对输入信号进行采样的采样电容器，用于对由电容器采样的信号进行积分的积分电容器和用于切换信号路径的多个开关构成。 控制电路控制开关的通/断状态以对采样电容器和积分电容器进行放电，并使环路滤波器重复采样操作和积分操作多次。 控制电路最后将采样电容器和积分电容器连接到与积分操作时间的状态相反的状态，并接通转换开关，使得A / D转换器对输出信号的输出信号进行A / D转换 环路滤波器。

    Drive circuit for power converter
    17.
    发明授权
    Drive circuit for power converter 有权

    公开(公告)号：US11750086B2

    公开(公告)日：2023-09-05

    申请号：US17547840

    申请日：2021-12-10

    Applicant: DENSO CORPORATION

    Inventor： Yasuaki Aoki ,  Tomohiro Nezuka ,  Akimasa Niwa

    IPC: H02M1/08 ,  H02M1/38 ,  H02M7/5387 ,  H03K17/16 ,  H02M1/00 ,  H02P27/06

    CPC classification number: H02M1/385 ,  H02M1/08 ,  H02M7/53871 ,  H03K17/165 ,  H02M1/0054 ,  H02P27/06 ,  H03K2217/0063 ,  H03K2217/0072

    Abstract: In a drive circuit, a differential circuit unit is configured such that resetting of an output voltage of the differential circuit unit is carried out, and the resetting of the output voltage of the differential circuit unit is cancelled. A value of the difference between first and second divided terminal voltages at a timing of cancelling the resetting is defined as a reference voltage. The differential circuit unit generates, as the output voltage, a product of a voltage change from a reference voltage and a predetermined amplification factor after cancelling of the resetting of the differential circuit unit. A signal generator generates a gate signal for the upper- and lower-arm switches in accordance with a value of the output voltage of the differential circuit unit while the upper- and lower-arm switches are in an off state.

    Vibration type gyroscope
    18.
    发明授权
    Vibration type gyroscope 有权

    公开(公告)号：US11262212B2

    公开(公告)日：2022-03-01

    申请号：US16362045

    申请日：2019-03-22

    Applicant: DENSO CORPORATION

    Inventor： Yoshikazu Furuta ,  Nobuaki Matsudaira ,  Tomohiro Nezuka

    IPC: G01C19/567 ,  G01C25/00

    Abstract: A gyroscope includes a MEMS sensor having a drive signal input terminal, a drive signal output terminal, and a sense signal output terminal. The gyroscope further includes a quadrature demodulator that demodulates a modulated sense signal and offset canceller circuits that cancel a direct current offset component included in an in-phase signal and a quadrature signal of the sense signal. The gyroscope has a quadrature error detector that detects a quadrature error based on the signals input from the offset canceller circuits and outputs an error signal. The gyroscope also has an IQ corrector circuit that receives the in-phase signal and the quadrature signal of the sense signal as inputs, and outputs a phase signal with a phase based on the error signal.

    Delta-sigma modulator, delta-sigma modulation type A/D converter and incremental delta-sigma modulation type A/D converter
    19.
    发明授权
    Delta-sigma modulator, delta-sigma modulation type A/D converter and incremental delta-sigma modulation type A/D converter 有权

    公开(公告)号：US10819360B2

    公开(公告)日：2020-10-27

    申请号：US16594587

    申请日：2019-10-07

    Applicant: DENSO CORPORATION

    Inventor： Kunihiko Nakamura ,  Tomohiro Nezuka

    IPC: H03M1/06 ,  H03M1/36 ,  H03M1/12

    Abstract: A ΔΣ modulator includes an input circuit having a sampling capacitor, an integration circuit, a quantizer and a D/A converter having a DAC capacitor. The input circuit takes in an analog input voltage in the sampling capacitor in a sampling period, and transfers a charge to the integration circuit in a holding period. The D/A converter takes in an analog potential, to which selection switches are connected in the sampling period based on a digital output of the quantizer, in the DAC capacitor, and subtracts a charge from the integration circuit in the holding period. At this time, since the input circuit and the D/A converter are set so that the holding periods do not overlap with each other, an error caused by the lowering of a feedback factor is suppressed.

    A/D converter
    20.
    发明授权
    A/D converter 有权

    公开(公告)号：US10581452B2

    公开(公告)日：2020-03-03

    申请号：US16196273

    申请日：2018-11-20

    Applicant: DENSO CORPORATION

    Inventor： Tomohiro Nezuka

    IPC: H03M3/00 ,  H03M1/14 ,  H03M3/02 ,  H03M1/12

    Abstract: An A/D converter includes: an integrator circuit executing ΔΣ modulation to an analog signal to be converted; an adder outputting an addition result of at least an output signal of the integrator circuit and a first reference signal as a reference signal of ΔΣ modulation; a quantizer receives an output signal of the integrator circuit, an output signal of the adder, and a second reference signal as a reference signal in cyclic A/D conversion to generate a result of quantization of the output signal of the integrator circuit and the output signal of the adder; and a controller is configured to switch between a ΔΣ modulation mode and a cyclic mode.

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