公开(公告)号：US20110124186A1

公开(公告)日：2011-05-26

申请号：US12947078

申请日：2010-11-16

Applicant: Anthony Renau ,  Ludovic Godet ,  Timothy J. Miller ,  Joseph C. Olson ,  Vikram Singh ,  James Buonodono ,  Frank Sinclair ,  Deepak A. Ramappa ,  Russell Low ,  Atul Gupta ,  Kevin M. Daniels

Inventor： Anthony Renau ,  Ludovic Godet ,  Timothy J. Miller ,  Joseph C. Olson ,  Vikram Singh ,  James Buonodono ,  Frank Sinclair ,  Deepak A. Ramappa ,  Russell Low ,  Atul Gupta ,  Kevin M. Daniels

IPC: H01L21/265 ,  G21K5/10

CPC classification number: B01J19/081 ,  H01J37/3171 ,  H01J37/32357 ,  H01J37/32422 ,  H01J37/32623 ,  H01J2237/0453 ,  H01J2237/1205 ,  H01L21/2236 ,  H01L31/022425 ,  H01L31/068 ,  H01L31/08 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

Abstract: A plasma processing apparatus comprises a plasma source configured to produce a plasma in a plasma chamber, such that the plasma contains ions for implantation into a workpiece. The apparatus also includes a focusing plate arrangement having an aperture arrangement configured to modify a shape of a plasma sheath of the plasma proximate the focusing plate such that ions exiting an aperture of the aperture arrangement define focused ions. The apparatus further includes a processing chamber containing a workpiece spaced from the focusing plate such that a stationary implant region of the focused ions at the workpiece is substantially narrower that the aperture. The apparatus is configured to create a plurality of patterned areas in the workpiece by scanning the workpiece during ion implantation.

Abstract translation: 等离子体处理装置包括等离子体源，其被配置为在等离子体室中产生等离子体，使得等离子体包含用于注入工件的离子。 该装置还包括聚焦板装置，该聚焦板装置具有孔结构，其被配置为修改离开聚焦板附近的等离子体鞘的等离子体鞘的形状，使得离开孔结构的孔的离子限定聚焦离子。 该设备还包括处理室，其包含与聚焦板间隔开的工件，使得在工件处的聚焦离子的固定注入区域基本上比孔更窄。 该装置被配置为通过在离子注入期间扫描工件来在工件中产生多个图案化区域。

公开(公告)号：US20100279479A1

公开(公告)日：2010-11-04

申请号：US12434364

申请日：2009-05-01

Applicant: Christopher R. Hatem ,  Helen L. Maynard ,  Deepak A. Ramappa

Inventor： Christopher R. Hatem ,  Helen L. Maynard ,  Deepak A. Ramappa

IPC: H01L21/30

CPC classification number: H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26593 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/7848

Abstract: A method is disclosed for enhancing tensile stress in the channel region of a semiconductor structure. The method includes performing one or more cold-carbon or molecular carbon ion implantation steps to implant carbon ions within the semiconductor structure to create strain layers on either side of a channel region. Raised source/drain regions are then formed above the strain layers, and subsequent ion implantation steps are used to dope the raised source/drain region. A millisecond anneal step activates the strain layers and the raised source/drain regions. The strain layers enhances carrier mobility within a channel region of the semiconductor structure, while the raised source/drain regions minimize reduction in strain in the strain layer caused by subsequent implantation of dopant ions in the raised source/drain regions.

Abstract translation: 公开了一种用于增强半导体结构的沟道区域中的拉伸应力的方法。 该方法包括执行一个或多个冷碳或分子碳离子注入步骤以在半导体结构内注入碳离子，以在沟道区的任一侧产生应变层。 然后在应变层上方形成升高的源极/漏极区域，并且随后的离子注入步骤用于掺杂升高的源极/漏极区域。 毫秒退火步骤激活应变层和升高的源极/漏极区域。 应变层增强了半导体结构的沟道区域内的载流子迁移率，而凸起的源极/漏极区域最小化了由于在升高的源极/漏极区域中随后注入掺杂剂离子引起的应变层中的应变减小。

公开(公告)号：US20100136781A1

公开(公告)日：2010-06-03

申请号：US12327336

申请日：2008-12-03

Applicant: Makarand R. Kulkarni ,  Deepak A. Ramappa

Inventor： Makarand R. Kulkarni ,  Deepak A. Ramappa

IPC: H01L21/768 ,  G03F1/00

CPC classification number: H01L21/76807 ,  H01L21/76816 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One embodiment of the present invention relates to a photolithography mask configured to form a metallization and via level utilizing a single lithography and etch process. More particularly, a photolithography mask comprising a mask via shape and one or more metal wire shapes is configured to produce both on-wafer metal lines and via levels. The mask via shape corresponds to an on-wafer photoresist via opening having a first critical dimension (CD). The one or more mask wire shapes correspond to one or more on-wafer photoresist wire openings respectively having a second CD. The first CD is larger than the second CD thereby providing a greater vertical etch rate for ILD exposed by the photoresist via opening than for ILD exposed by the one or more photoresist wire openings. This difference in CD results in a via extending vertically below the metal wire level, thereby making physical contact with underlying metal.

Abstract translation: 本发明的一个实施例涉及一种配置成利用单个光刻和蚀刻工艺形成金属化和通孔级的光刻掩模。 更具体地，包括掩模通孔形状和一个或多个金属线形状的光刻掩模被配置为产生晶片上金属线和通孔级。 掩模通孔形状对应于具有第一临界尺寸（CD）的经晶片上的光刻胶通孔开口。 一个或多个掩模线形状对应于分别具有第二CD的一个或多个晶片上的光致抗蚀剂丝线开口。 第一CD大于第二CD，从而为由光致抗蚀剂经由开口曝光的ILD提供比通过一个或多个光致抗蚀剂线开口暴露的ILD更大的垂直蚀刻速率。 CD中的这种差异导致在金属线水平面垂直延伸的通孔，从而与底层金属物理接触。

公开(公告)号：US07601629B2

公开(公告)日：2009-10-13

申请号：US11312926

申请日：2005-12-20

Applicant: Deepak A. Ramappa ,  Richard L. Guldi ,  Asad Haider ,  Frank Poag

Inventor： Deepak A. Ramappa ,  Richard L. Guldi ,  Asad Haider ,  Frank Poag

IPC: H01L21/4763

CPC classification number: H01L23/5222 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76835 ,  H01L21/76843 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention provides a method of fabricating a semiconductive device [200]. In this embodiment, the method comprises depositing a hydrocarbon layer [294] over a semiconductive substrate, forming an interconnect structure [295, 297] within the hydrocarbon layer [294], and removing the hydrocarbon layer [294] by sublimation.

Abstract translation: 本发明提供一种制造半导体器件的方法[200]。 在该实施例中，该方法包括在半导体衬底上沉积烃层，在烃层[294]内形成互连结构[295,297]，并通过升华除去烃层[294]。

公开(公告)号：US20090170221A1

公开(公告)日：2009-07-02

申请号：US11965972

申请日：2007-12-28

Applicant: Jeannette Michelle Jacques ,  Deepak A. Ramappa

Inventor： Jeannette Michelle Jacques ,  Deepak A. Ramappa

IPC: H01L21/66

CPC classification number: H01L21/76808 ,  H01L21/02063 ,  H01L21/76814

Abstract: Methods for forming dual damascene interconnect structures are provided. The methods incorporate an ashing operation comprising a first ash operation and a second overash operation. The ashing operation is performed prior to etching of an etch stop layer. The operation removes residue from a cavity formed during formation of the interconnect structure and facilitates better CD control without altering the cavity profiles.

Abstract translation: 提供了形成双镶嵌互连结构的方法。 该方法包括灰化操作，其包括第一灰分操作和第二溢出操作。 灰蚀操作在刻蚀停止层之前进行。 该操作从在形成互连结构期间形成的空腔中去除残留物，并且便于更好的CD控制而不改变空腔轮廓。

公开(公告)号：US09062367B2

公开(公告)日：2015-06-23

申请号：US13608709

申请日：2012-09-10

Applicant: Christopher R. Hatem ,  Ludovic Godet ,  Louis Steen ,  Deepak A. Ramappa

Inventor： Christopher R. Hatem ,  Ludovic Godet ,  Louis Steen ,  Deepak A. Ramappa

IPC: C23C14/48 ,  C23C14/12 ,  C23C14/04 ,  H01J37/32

CPC classification number: C23C14/048 ,  H01J37/32412

Abstract: A surface of an insulating workpiece is implanted to form either hydrophobic or hydrophilic implanted regions. A conductive coating is deposited on the workpiece. The coating may be a polymer in one instance. This coating preferentially forms either on the implanted regions if these implanted regions are hydrophilic or on the non-implanted regions if the implanted regions are hydrophobic.

Abstract translation: 植入绝缘工件的表面以形成疏水或亲水注入区域。 导电涂层沉积在工件上。 在一种情况下，涂层可以是聚合物。 如果这些注入区域是亲水的，则该涂层优选地形成在注入区域上，或者如果注入的区域是疏水的，则优选地形成在非注入区域上。

公开(公告)号：US08716155B2

公开(公告)日：2014-05-06

申请号：US13610322

申请日：2012-09-11

Applicant: Deepak A. Ramappa ,  Kyu-Ha Shim

Inventor： Deepak A. Ramappa ,  Kyu-Ha Shim

IPC: H01L21/469

CPC classification number: H01L21/28282 ,  H01L29/4234 ,  H01L29/513

Abstract: Methods of improving charge trapping are disclosed. One such method includes forming an oxide-nitride-oxide tunnel stack and a silicon nitride layer on the oxide-nitride-oxide tunnel stack. This silicon nitride layer is implanted with ions. These ions may function as electron traps or as fields. The silicon nitride layer may be part of a flash memory device.

Abstract translation: 公开了改善电荷俘获的方法。 一种这样的方法包括在氧化物 - 氮化物 - 氧化物隧道叠层上形成氧化物 - 氮化物 - 氧化物隧道堆叠和氮化硅层。 该氮化硅层被注入离子。 这些离子可以用作电子阱或场。 氮化硅层可以是闪存器件的一部分。

公开(公告)号：US08614143B2

公开(公告)日：2013-12-24

申请号：US12327336

申请日：2008-12-03

Applicant: Makarand R. Kulkarni ,  Deepak A. Ramappa

Inventor： Makarand R. Kulkarni ,  Deepak A. Ramappa

IPC: H01L21/4763

CPC classification number: H01L21/76807 ,  H01L21/76816 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One embodiment of the present invention relates to a photolithography mask configured to form a metallization and via level utilizing a single lithography and etch process. More particularly, a photolithography mask comprising a mask via shape and one or more metal wire shapes is configured to produce both on-wafer metal lines and via levels. The mask via shape corresponds to an on-wafer photoresist via opening having a first critical dimension (CD). The one or more mask wire shapes correspond to one or more on-wafer photoresist wire openings respectively having a second CD. The first CD is larger than the second CD thereby providing a greater vertical etch rate for ILD exposed by the photoresist via opening than for ILD exposed by the one or more photoresist wire openings. This difference in CD results in a via extending vertically below the metal wire level, thereby making physical contact with underlying metal.

Abstract translation: 本发明的一个实施例涉及一种配置成利用单个光刻和蚀刻工艺形成金属化和通孔级的光刻掩模。 更具体地，包括掩模通孔形状和一个或多个金属线形状的光刻掩模被配置为产生晶片上金属线和通孔级。 掩模通孔形状对应于具有第一临界尺寸（CD）的经晶片上的光刻胶通孔开口。 一个或多个掩模线形状对应于分别具有第二CD的一个或多个晶片上的光致抗蚀剂丝线开口。 第一CD大于第二CD，从而为由光致抗蚀剂经由开口暴露的ILD提供比通过一个或多个光致抗蚀剂线开口暴露的ILD更大的垂直蚀刻速率。 CD中的这种差异导致在金属线水平面垂直延伸的通孔，从而与底层金属物理接触。

公开(公告)号：US08592230B2

公开(公告)日：2013-11-26

申请号：US13091289

申请日：2011-04-21

Applicant: Deepak A. Ramappa ,  Ludovic Godet

Inventor： Deepak A. Ramappa ,  Ludovic Godet

IPC: H01L21/00

CPC classification number: H01L21/00 ,  C23C14/042 ,  C23C14/48 ,  C23C16/02 ,  C23C16/04 ,  C23C16/50 ,  H01L31/0682 ,  H01L31/0747 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

Abstract: A method of patterning a substrate includes providing a focusing plate adjacent to a plasma chamber containing a plasma, the focusing plate configured to extract ions from the plasma through at least one aperture that provides focused ions towards the substrate. The method further includes directing first ions through the at least one aperture to one or more first regions of the substrate so as to condense first gaseous species provided in ambient of the substrate on the one or more first regions of the substrate.

Abstract translation: 图案化衬底的方法包括提供邻近包含等离子体的等离子体室的聚焦板，该聚焦板被配置为通过至少一个孔向等离子体提取离子，所述孔向衬底提供聚焦离子。 该方法还包括将第一离子引导通过至少一个孔到基底的一个或多个第一区域，以便在衬底的一个或多个第一区域上冷凝在衬底环境中提供的第一气态物质。

公开(公告)号：US08507298B2

公开(公告)日：2013-08-13

申请号：US13310318

申请日：2011-12-02

Applicant: Deepak A. Ramappa

Inventor： Deepak A. Ramappa

IPC: H01L21/00

CPC classification number: H01L31/0682 ,  H01L21/76802 ,  H01L31/022441 ,  Y02E10/547

Abstract: At least part of a dielectric layer is implanted to form implanted regions. The implanted regions affect the etch rate of the dielectric layer during the formation of the openings through the dielectric layer. Metal contacts may be formed within these openings. The dielectric layer, which may be SiO2 or other materials, may be part of a solar cell or other device.

Abstract translation: 介电层的至少一部分被植入以形成植入区域。 注入区域在通过电介质层形成开口期间影响电介质层的蚀刻速率。 可以在这些开口内形成金属接触。 可以是SiO 2或其它材料的电介质层可以是太阳能电池或其他器件的一部分。