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    Integrated semiconductor memory and fabrication method
    11.
    发明授权
    Integrated semiconductor memory and fabrication method 有权
    集成半导体存储器和制造方法

    公开(公告)号：US06750098B2

    公开(公告)日：2004-06-15

    申请号：US10619970

    申请日：2003-07-15

    Applicant: Till Schlösser ,  Dirk Manger

    Inventor： Till Schlösser ,  Dirk Manger

    IPC: H01L218242

    CPC classification number: H01L27/10864 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891 ,  H01L29/66666

    Abstract: In semiconductor memories having a surrounding gate configuration, webs, i.e. vertical rectangular pillars made of substrate material, are formed at the surface of a semiconductor substrate and are surrounded by the gate electrodes in a lower region. Conventionally, it is not possible for word lines to make contact with the gate electrodes in the lower region of the webs without at the same time electrically influencing substrate regions at a higher level in the webs or short-circuiting bit lines from their sidewalls, unless complicated methods requiring additional lithography steps are used. A method for the self-aligning, selective contact-connection of the peripheral gate electrodes is performed with the aid of an insulation layer having a smaller layer thickness than the peripheral gate electrodes.

    Abstract translation: 在具有围绕栅极结构的半导体存储器中，在半导体衬底的表面上形成由衬底材料制成的腹板，即垂直矩形柱，并且在下部区域中由栅电极包围。 通常，字线不可能与幅材的下部区域中的栅极电极接触，而不会同时在幅材或短路位线从其侧壁电位影响衬底区域的较高水平，除非 使用需要额外光刻步骤的复杂方法。 借助于具有比外围栅极电极更薄的层厚度的绝缘层来执行外围栅电极的自对准，选择性接触连接的方法。

    Vertical device with sidewall spacer, methods of forming sidewall spacers and field effect transistors, and patterning method
    12.
    发明授权
    Vertical device with sidewall spacer, methods of forming sidewall spacers and field effect transistors, and patterning method 失效
    具有侧壁间隔件的垂直装置，形成侧壁间隔物的方法和场效应晶体管，以及图案化方法

    公开(公告)号：US07678679B2

    公开(公告)日：2010-03-16

    申请号：US11414553

    申请日：2006-05-01

    Applicant: Dirk Manger ,  Jyoti Gupta ,  Christoph Ludwig ,  Hans Lindemann

    Inventor： Dirk Manger ,  Jyoti Gupta ,  Christoph Ludwig ,  Hans Lindemann

    IPC: H01L21/3205 ,  H01L21/4763

    CPC classification number: H01L21/28247 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

    Abstract: A growth material that grows selectively on the vertical sidewalls of a vertical device forms sidewall spacers on substantially vertical sidewalls of the vertical device that is disposed on a horizontal substrate surface of a semiconductor substrate. A spacer-like seed liner may be provided on the vertical sidewalls of the vertical device to control selective growth. The vertical device may be a gate electrode of a field effect transistor (FET). With selectively grown sidewall spacers, heavily doped contact regions of the FET may be precisely spaced apart from the gate electrode. The distance of the heavily doped contact regions to the gate electrode does not depend from the height of the gate electrode. Distances of more than 150 nm between the heavily doped contact region and the gate electrode may be achieved so as to facilitate the formation of, for example, DMOS devices.

    Abstract translation: 选择性地在垂直装置的垂直侧壁上生长的生长材料在垂直装置的基本上垂直的侧壁上形成侧壁间隔物，其设置在半导体衬底的水平衬底表面上。 可以在垂直装置的垂直侧壁上设置间隔物种子衬垫，以控制选择性生长。 垂直装置可以是场效应晶体管（FET）的栅电极。 利用选择性地生长的侧壁间隔物，FET的重掺杂接触区域可以与栅电极精确地间隔开。 重掺杂的接触区域与栅电极的距离不取决于栅电极的高度。 可以实现重掺杂接触区域和栅电极之间超过150nm的距离，以便于例如DMOS器件的形成。

    Methods of Manufacturing a Semiconductor Device
    14.
    发明申请
    Methods of Manufacturing a Semiconductor Device 审中-公开
    制造半导体器件的方法

    公开(公告)号：US20090239314A1

    公开(公告)日：2009-09-24

    申请号：US12051932

    申请日：2008-03-20

    Applicant: Martin Haberjahn ,  Sascha Dieter ,  Andrea Graf ,  Christoph Noelscher ,  Dirk Manger ,  Stephan Wege

    Inventor： Martin Haberjahn ,  Sascha Dieter ,  Andrea Graf ,  Christoph Noelscher ,  Dirk Manger ,  Stephan Wege

    IPC: H01L21/66

    CPC classification number: H01L22/12 ,  H01L22/26

    Abstract: Methods of manufacturing a semiconductor device and an apparatus for the manufacturing of semiconductor devices are provided. An embodiment regards providing a process which changes the volume of at least one layer of a semiconductor substrate or of at least one layer deposited on the semiconductor substrate, and measuring a change in volume of such at least one layer using fluorescence. In another embodiment, a change in volume of such at least one layer is measured using reflection of electromagnetic waves.

    Abstract translation: 提供制造半导体器件的方法和用于制造半导体器件的设备。 实施例涉及提供一种改变至少一层半导体衬底或沉积在半导体衬底上的至少一层的层的体积，并使用荧光来测量这样的至少一层的体积变化的过程。 在另一个实施例中，使用电磁波的反射来测量这样的至少一层的体积变化。

    Memory cell array and method of manufacturing the same
    15.
    发明授权
    Memory cell array and method of manufacturing the same 有权
    存储单元阵列及其制造方法

    公开(公告)号：US07473952B2

    公开(公告)日：2009-01-06

    申请号：US11118768

    申请日：2005-05-02

    Applicant: Dirk Manger ,  Stefan Slesazeck ,  Stefan Tegen ,  Klaus Muemmler ,  Alexander Sieck

    Inventor： Dirk Manger ,  Stefan Slesazeck ,  Stefan Tegen ,  Klaus Muemmler ,  Alexander Sieck

    IPC: H01L27/108 ,  H01L29/94

    CPC classification number: H01L27/10876 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10891

    Abstract: A memory cell array includes a plurality of active areas in which a plurality of memory cells are formed. A memory cell includes a storage capacitor, a transistor at least partially formed in a semiconductor substrate with a substrate surface, the transistor including a first source/drain region. A second source/drain region being formed adjacent to the substrate surface, a channel region connecting the first and second source/drain regions. The first source/drain region is formed adjacent to the substrate surface. The channel region is disposed in the semiconductor substrate, and a gate electrode. Rows of the active areas are separated from each other by isolation grooves that extend along a first direction. A first and a second word lines are disposed on either lateral sides of each of the rows of active areas. The first and the second word lines are connected with each other via the gate electrodes of the transistors of the corresponding row of active areas.

    Abstract translation: 存储单元阵列包括其中形成有多个存储单元的多个有效区域。 存储单元包括存储电容器，至少部分地形成在具有衬底表面的半导体衬底中的晶体管，所述晶体管包括第一源极/漏极区域。 与衬底表面相邻形成的第二源极/漏极区域，连接第一和第二源极/漏极区域的沟道区域。 第一源极/漏极区域邻近于衬底表面形成。 沟道区设置在半导体衬底和栅电极中。 有源区域的行通过沿着第一方向延伸的隔离槽相互分离。 第一和第二字线被布置在每行活动区域的任一侧面上。 第一和第二字线经由相应行的有效区域的晶体管的栅电极相互连接。

    Non-volatile memory array and method of fabricating the same
    17.
    发明申请
    Non-volatile memory array and method of fabricating the same 审中-公开
    非易失性存储器阵列及其制造方法

    公开(公告)号：US20070269948A1

    公开(公告)日：2007-11-22

    申请号：US11436884

    申请日：2006-05-19

    Applicant: Dirk Manger

    Inventor： Dirk Manger

    IPC: H01L21/336

    CPC classification number: H01L27/11568 ,  H01L27/115

    Abstract: A two-bits-per-cell flash memory cell is based on a localized trapping storage mechanism. The memory cell may be programmed via a hot hole injection mechanism and erased via a Fowler-Nordheim electron tunneling mechanism. The memory cells are arranged according to a virtual-ground wiring scheme. Gate structures of the memory cells are arranged in columns, and the widths of the columns are essentially equal to the distance between the columns. Bit lines elongate in pairs between the columns of memory cells and connect corresponding impurity regions being associated to one of the columns of memory cells. Separation devices separating the bit lines of each pair of bit lines are formed symmetrically to the edges of the neighboring columns of memory cells. Program cross-talk issues, concerning memory cells sharing the same bit line, may be avoided while memory cell size remains essentially unaffected.

    Abstract translation: 每单元两位闪存单元基于局部捕获存储机制。 可以通过热空穴注入机构对存储单元进行编程，并通过Fowler-Nordheim电子隧穿机构擦除。 存储单元根据虚拟接地布线方案布置。 存储器单元的栅极结构被布置成列，并且列的宽度基本上等于列之间的距离。 位线在存储器单元的列之间成对延伸，并且连接与存储器单元的列之一相关联的相应杂质区。 分离每对位线的位线的分离装置对称地形成存储单元的相邻列的边缘。 关于共享相同位线的存储器单元的程序串扰问题可能被避免，而存储单元大小基本上不受影响。

    Memory cell array and method of manufacturing the same
    19.
    发明申请
    Memory cell array and method of manufacturing the same 有权

    公开(公告)号：US20060244024A1

    公开(公告)日：2006-11-02

    申请号：US11118768

    申请日：2005-05-02

    Applicant: Dirk Manger ,  Stefan Slesazeck ,  Stefan Tegen ,  Klaus Muemmler ,  Alexander Sieck

    Inventor： Dirk Manger ,  Stefan Slesazeck ,  Stefan Tegen ,  Klaus Muemmler ,  Alexander Sieck

    IPC: H01L29/94

    CPC classification number: H01L27/10876 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10891

    Abstract: A memory cell array includes a plurality of active areas in which a plurality of memory cells are formed. A memory cell includes a storage capacitor, a transistor at least partially formed in a semiconductor substrate with a substrate surface, the transistor including a first source/drain region. A second source/drain region being formed adjacent to the substrate surface, a channel region connecting the first and second source/drain regions. The first source/drain region is formed adjacent to the substrate surface. The channel region is disposed in the semiconductor substrate, and a gate electrode. Rows of the active areas are separated from each other by isolation grooves that extend along a first direction. A first and a second word lines are disposed on either lateral sides of each of the rows of active areas. The first and the second word lines are connected with each other via the gate electrodes of the transistors of the corresponding row of active areas.

    Integrated semiconductor memory with wordlines conductively connected to one another in pairs
    20.
    发明授权
    Integrated semiconductor memory with wordlines conductively connected to one another in pairs 失效
    集成半导体存储器，其字线彼此成对地导电连接

    公开(公告)号：US06956260B2

    公开(公告)日：2005-10-18

    申请号：US10463019

    申请日：2003-06-17

    Applicant: Dirk Manger ,  Till Schlösser ,  Martin Popp ,  Michael Sesterhenn

    Inventor： Dirk Manger ,  Till Schlösser ,  Martin Popp ,  Michael Sesterhenn

    IPC: H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC classification number: H01L27/10864 ,  H01L27/10841 ,  H01L27/10876 ,  H01L27/10891

    Abstract: In semiconductor memories, in particular DRAMs, the memory cells of which have vertical transistors at vertical lands formed from substrate material, gate electrodes are formed as spacers which run around the land. The gate electrodes of adjacent memory cells conventionally have to be retroactively connected to form word lines. It is known to fill spaces between adjacent lands with an oxide, with the result that the spacers are formed directly as word lines but only cover two side walls of a land. Two transistors which are connected in parallel are formed at these side walls instead of a single transistor, since the gate electrode does not run around the land. The invention proposes a method for fabricating a semiconductor memory in which all four side walls of a land are covered by the word lines and at the same time lands of adjacent memory cells are connected to one another by the word lines.

    Abstract translation: 在半导体存储器中，特别是DRAM，其存储单元在由衬底材料形成的垂直焊盘处具有垂直晶体管，栅电极形成为围绕焊盘运行的间隔件。 相邻存储单元的栅电极通常必须追溯地连接以形成字线。 已知用相邻的焊盘之间的空间填充氧化物，结果是间隔件直接形成为字线，而仅覆盖焊盘的两个侧壁。 并联连接的两个晶体管形成在这些侧壁而不是单个晶体管，因为栅电极不会绕着焊盘运行。 本发明提出一种半导体存储器的制造方法，其中，由字线覆盖焊盘的四个侧壁，同时通过字线将相邻存储单元的焊盘相互连接。

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