公开(公告)号：US20240419361A1

公开(公告)日：2024-12-19

申请号：US18812443

申请日：2024-08-22

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. ALAM ,  Iftekhar RAHMAN ,  Pedro SANCHEZ

IPC: G06F3/06

Abstract: The present disclosure is drawn to, among other things, a method for programming a memory device comprising a plurality of memory arrays. The method may include receiving a command to program one or more of the plurality of memory arrays and programming the one or more of the plurality of memory arrays based on the command. The method may optionally include erasing the one or more of the plurality of memory arrays prior to the programming.

公开(公告)号：US20230403011A1

公开(公告)日：2023-12-14

申请号：US18329793

申请日：2023-06-06

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. ALAM ,  Sanjeev AGGARWAL

IPC: H03K19/1776 ,  H10B61/00 ,  H01L23/498 ,  H10N50/10 ,  H01L23/48

CPC classification number: H03K19/1776 ,  H10B61/00 ,  H01L23/49816 ,  H10N50/10 ,  H01L23/481

Abstract: A memory device includes a printed circuit board, a magnetoresistive random-access memory (MRAM) device coupled to the printed circuit board, a controller or control circuitry, wherein the controller or control circuitry is integrated into, embedded in, or otherwise incorporated into the MRAM device, and a field programmable gate array (FPGA) coupled to the printed circuit board and in communication with the controller or control circuitry.

公开(公告)号：US20230267982A1

公开(公告)日：2023-08-24

申请号：US17847265

申请日：2022-06-23

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. ALAM

IPC: G11C11/16 ,  H01L23/525 ,  H01L43/08 ,  H01L43/02

CPC classification number: G11C11/1695 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1657 ,  H01L23/5252 ,  H01L43/08 ,  H01L43/02

Abstract: The present disclosure is drawn to, among other things, an antifuse circuit. The antifuse circuit includes a plurality of antifuse bitcells and a reference resistor. Each antifuse bitcell includes two or more memory bits and a reference resistor. The two or more memory bits are configured to be in a programmed state and at least one unprogrammed state.

公开(公告)号：US20220180913A1

公开(公告)日：2022-06-09

申请号：US17113595

申请日：2020-12-07

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. ALAM ,  Yaojun ZHANG ,  Frederick NEUMEYER

IPC: G11C11/16

Abstract: The present disclosure is drawn to a magnetoresistive device including an array of memory cells arranged in rows and columns, each memory cell comprising a magnetic tunnel junction, each row comprising a word line, and each column comprising a bit line; a column select device that selects a bit line. The magnetoresistive device also includes a sense amplifier comprising a first input corresponding to a selected bit line, a second input corresponding to a reference bit line, and a data output. The plurality of columns comprise a reference column, the reference column comprising a conductive element coupled to the magnetic tunnel junctions in the reference column.

公开(公告)号：US20200235288A1

公开(公告)日：2020-07-23

申请号：US16744963

申请日：2020-01-16

Applicant: Everspin Technologies, Inc.

Inventor： Sumio IKEGAWA ,  Han Kyu LEE ,  Sanjeev AGGARWAL ,  Jijun SUN ,  Syed M. ALAM ,  Thomas ANDRE

IPC: H01L43/04 ,  H01L27/22 ,  H01L43/06 ,  H01L43/10 ,  H01L43/14

Abstract: The present disclosure is drawn to, among other things, a magnetoresistive device and a magnetoresistive memory comprising a plurality of such magnetoresistive devices. In some aspects, a magnetoresistive device may include a magnetically fixed region, a magnetically free region above or below the magnetically fixed region, and an intermediate region positioned between the magnetically fixed region and the magnetically free region, wherein the intermediate region includes a first dielectric material. The magnetoresistive device may also include encapsulation layers formed on opposing side walls of the magnetically free region, wherein the encapsulation layers include the first dielectric material.

公开(公告)号：US20190087250A1

公开(公告)日：2019-03-21

申请号：US16174557

申请日：2018-10-30

Applicant: Everspin Technologies, Inc.

Inventor： Jon SLAUGHTER ,  Dimitri HOUSSAMEDDINE ,  Thomas ANDRE ,  Syed M. ALAM

IPC: G06F11/07 ,  G11C11/16

Abstract: A method is provided for healing reset errors for a magnetic memory using destructive read with selective write-back, including for example, a self-referenced read of spin-torque bits in an MRAM. Memory cells are prepared for write back by one of identifying memory cells determined in error using an error correcting code and inverting the inversion bit for those memory cells determined in error identifying memory cells determined in error using an error correcting code and resetting a portion of the memory cells to the first state; and resetting one or more memory cells to the first state.

公开(公告)号：US20180314635A1

公开(公告)日：2018-11-01

申请号：US15499136

申请日：2017-04-27

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Syed M. ALAM

IPC: G06F12/0804 ,  G06F12/0893 ,  G06F3/06 ,  G11C11/4096 ,  G11C11/4076

CPC classification number: G11C16/22 ,  G11C2207/2245 ,  G11C2207/2254

Abstract: A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed. Calibration and testing sequences are also supported in which a non-destructive mode preserves data stored in a non-volatile memory array and status bits used to indicate open pages are cleared so later inadvertent delayed write-back operations as a result of the calibration or testing do not corrupt the non-volatile data.

公开(公告)号：US20170301384A1

公开(公告)日：2017-10-19

申请号：US15636970

申请日：2017-06-29

Applicant: Everspin Technologies, Inc.

Inventor： Thomas ANDRE ,  Syed M. ALAM ,  Chitra SUBRAMANIAN

IPC: G11C11/16 ,  G11C7/06 ,  G11C7/02 ,  G11C13/00

CPC classification number: G11C11/1675 ,  G11C7/02 ,  G11C7/065 ,  G11C11/16 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693 ,  G11C2013/0057 ,  G11C2207/002

Abstract: An apparatus used in a self-referenced read of a memory bit cell includes circuitry including a plurality of transistors that includes an NMOS-follower transistor for applying a read voltage to a first end of the bit cell. An offset current is applied by an offset current transistor. A transmission gate allows for isolation of a capacitor used to store a sample voltage corresponding to the read voltage applied across the memory bit cell.

公开(公告)号：US20250029645A1

公开(公告)日：2025-01-23

申请号：US18909363

申请日：2024-10-08

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. ALAM

IPC: G11C11/16 ,  H01L23/525 ,  H10N50/10 ,  H10N50/80

Abstract: The present disclosure is drawn to, among other things, an antifuse circuit. The antifuse circuit includes a plurality of antifuse bitcells and a reference resistor. Each antifuse bitcell includes two or more memory bits and a reference resistor. The two or more memory bits are configured to be in a programmed state and at least one unprogrammed state.

公开(公告)号：US20240420796A1

公开(公告)日：2024-12-19

申请号：US18739969

申请日：2024-06-11

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. ALAM ,  Jacob T. WILLIAMS ,  Michael A. SADD ,  Kerry Joseph NAGEL ,  Sumio IKEGAWA ,  Frederick B. MANCOFF ,  Sanjeev AGGARWAL

IPC: G11C29/00 ,  G11C29/30 ,  G11C29/32

Abstract: A memory device including a first configuration bit group including a plurality of bits, the plurality of bits including: a plurality of configuration bits; at least one redundant configuration bit; a plurality of configuration bit multiplexers each configured to receive (i) a first input from a first bit in the plurality of bits and/or a second input from a second bit in the plurality of bits and (ii) a third input from a decoder, each of the first, second, and third inputs indicating a respective logical state, wherein the logical state includes a first state or a second state; and wherein, based on the logical state of the third input received from the decoder, each configuration bit multiplexer is configured to output: the logical state of the first input from the first bit, or the logical state of the second input from the second bit.