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28 条记录 (耗时 0.021 秒)

    Semiconductor surface measurement system and method
    11.
    发明授权
    Semiconductor surface measurement system and method 失效
    半导体表面测量系统及方法

    公开(公告)号：US5956148A

    公开(公告)日：1999-09-21

    申请号：US989904

    申请日：1997-12-12

    申请人： Francis G. Celii

    发明人： Francis G. Celii

    IPC分类号： G01B11/06 ,  G01J4/00

    CPC分类号： G01B11/0641

    摘要： A semiconductor surface measurement system (100) is disclosed. In this system, a plurality of wafers (106), each having an exposed surface, are held by a wafer positioning system (104), which sequentially moves the wafers into a measurement zone. A wafer position detection system (124) detects the position of a selected wafer, and generates an output signal indicating the position of the selected wafer. A surface measurement apparatus (114 through 121, 130 through 142) measures a property of the exposed surface of the selected wafer (106) in response to the output signal of the wafer position detection system (124) when the selected wafer is in the measurement zone. The disclosed surface measurement system (100)may be used to gather real-time data concerning surface properties such as composition, roughness and epilayer thickness during multi-wafer semiconductor processing.

    摘要翻译： 公开了半导体表面测量系统（100）。 在该系统中，每个具有暴露表面的多个晶片（106）由晶片定位系统（104）保持，晶片定位系统（104）将晶片顺序地移动到测量区域中。 晶片位置检测系统（124）检测所选晶片的位置，并产生指示所选晶片的位置的输出信号。 当所选晶片处于测量状态时，表面测量装置（114至121,130至142）响应于晶片位置检测系统（124）的输出信号测量所选晶片（106）的暴露表面的性质 区。 公开的表面测量系统（100）可以用于收集关于多晶片半导体处理期间的表面特性（例如组成，粗糙度和外延层厚度）的实时数据。

    Defect and etch rate control in trench etch for dual damascene patterning of low-k dielectrics
    12.
    发明授权
    Defect and etch rate control in trench etch for dual damascene patterning of low-k dielectrics 有权
    对于低k电介质的双镶嵌图案，沟槽蚀刻中的缺陷和蚀刻速率控制

    公开(公告)号：US06455411B1

    公开(公告)日：2002-09-24

    申请号：US09947966

    申请日：2001-09-06

    申请人： Ping Jiang ,  Francis G. Celii ,  Kenneth J. Newton ,  Hiromi Sakima

    发明人： Ping Jiang ,  Francis G. Celii ,  Kenneth J. Newton ,  Hiromi Sakima

    IPC分类号： H01L21308

    CPC分类号： H01L21/76808 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144

    摘要： A dual damascene process for low-k or ultra low-k dielectric such as organo-silicate glass (OSG). After the via (112) etch, a trench (121) is etched in the OSG layer (108) using a less-polymerizing fluorocarbon added to an etch chemistry comprising a fluorocarbon and low N2/Ar ratio. The low N2/Ar ratio controls ridge formation during the trench etch. The combination of a less-polymerizing fluorocarbon with a higher-polymerizing fluorocarbon achieves a high etch rate and defect-free conditions.

    摘要翻译： 用于低k或超低k电介质的双镶嵌工艺，如有机硅酸盐玻璃（OSG）。 在通孔（112）蚀刻之后，使用添加到包含碳氟化合物和低N 2 / Ar比的蚀刻化学品中的较少聚合的碳氟化合物在OSG层（108）中蚀刻沟槽（121）。 低N 2 / Ar比控制沟槽蚀刻期间的脊形成。 低聚碳氟化合物与较高聚合碳氟化合物的组合实现了高蚀刻速率和无缺陷条件。

    Semiconductor growth method with thickness control
    13.
    发明授权
    Semiconductor growth method with thickness control 失效
    具有厚度控制的半导体生长方法

    公开(公告)号：US5756375A

    公开(公告)日：1998-05-26

    申请号：US664940

    申请日：1996-06-14

    申请人： Francis G. Celii ,  Walter M. Duncan ,  Tae S. Kim

    发明人： Francis G. Celii ,  Walter M. Duncan ,  Tae S. Kim

    IPC分类号： H01L21/205 ,  H01L21/66 ,  H01L21/203

    CPC分类号： B24B37/013 ,  H01L22/26 ,  H01L21/02392 ,  H01L21/02463 ,  H01L21/02546

    摘要： Molecular beam epitaxy (202) with growing layer thickness and doping control (206) by feedback of sensor signals such as spectrosceopic ellipsometer signals based on a process model. Examples include III-V compound structures with multiple AlAs, InGaAs, and InAs layers as used in resonant tunneling diodes and hetrojunction bipolar transistors with doped and undoped GaAs layers, AlGaAs and InGaAs.

    摘要翻译： 通过基于过程模型的传感器信号（例如光谱椭偏仪信号）的反馈，分子束外延（202）具有增长的层厚度和掺杂控制（206）。 实例包括具有多个AlAs，InGaAs和InAs层的III-V化合物结构，其用于具有掺杂和未掺杂的GaAs层，AlGaAs和InGaAs的谐振隧道二极管和掺杂双极晶体管。

    Etching systems and processing gas specie modulation
    16.
    发明授权
    Etching systems and processing gas specie modulation 有权
    蚀刻系统和加工气体调制

    公开(公告)号：US07560385B2

    公开(公告)日：2009-07-14

    申请号：US10263981

    申请日：2002-10-03

    申请人： Francis G. Celii ,  Ping Jiang

    发明人： Francis G. Celii ,  Ping Jiang

    IPC分类号： H01L21/302

    CPC分类号： H01L21/31116

    摘要： A method and system for etching a substrate control selectivity of the etch process by modulating the gas specie of the reactants. The gas specie selectively form and etch a buffer layer that protects underlying etch stop materials thereby providing highly selective etch processes.

    摘要翻译： 用于通过调节反应物的气体样品蚀刻蚀刻工艺的衬底控制选择性的方法和系统。 气体选择性地形成和蚀刻缓冲层，其保护潜在的蚀刻停止材料，从而提供高度选择性的蚀刻工艺。

    Photolithographic method for fabricating organic light-emitting diodes
    17.
    发明授权
    Photolithographic method for fabricating organic light-emitting diodes 有权
    用于制造有机发光二极管的光刻方法

    公开(公告)号：US06506616B1

    公开(公告)日：2003-01-14

    申请号：US09714472

    申请日：2000-11-16

    申请人： Tae S. Kim ,  Francis G. Celii ,  Simon J. Jacobs

    发明人： Tae S. Kim ,  Francis G. Celii ,  Simon J. Jacobs

    IPC分类号： H01L2100

    CPC分类号： H01L51/56 ,  H01L51/0018 ,  H01L51/5253

    摘要： A method of photolithographically patterning an organic semiconductor device, comprising the steps of protecting the organic layer of the device by depositing a metal layer thereon, depositing and patterning a photoresist layer on said metal layer, and selectively etching the exposed areas to pattern said metal layer and said organic layer. Specifically, the disclosed method provides the photolithographic fabrication of organic light emitting diodes (OLEDs) and organic lasers diodes (OLDs).

    摘要翻译： 一种光刻图案化有机半导体器件的方法，包括以下步骤：通过在其上沉积金属层来保护器件的有机层，在所述金属层上沉积和图案化光致抗蚀剂层，并且选择性地蚀刻暴露的区域以图案化所述金属层 并说有机层。 具体地，所公开的方法提供有机发光二极管（OLED）和有机激光二极管（OLD）的光刻制造。

    Process for monitoring the thickness of layers in a microelectronic device
    18.
    发明授权
    Process for monitoring the thickness of layers in a microelectronic device 有权

    公开(公告)号：US06605482B2

    公开(公告)日：2003-08-12

    申请号：US09975637

    申请日：2001-10-11

    申请人： Francis G. Celii ,  Maureen A. Hanratty ,  Katherine E. Violette ,  Rick L. Wise

    发明人： Francis G. Celii ,  Maureen A. Hanratty ,  Katherine E. Violette ,  Rick L. Wise

    IPC分类号： H01L2166

    CPC分类号： G01N21/55

    摘要： A method of determining the thickness of a thickness of a first layer of material in a semiconductor device using a reflectometer, the first layer of material being disposed outwardly from a second layer of material, the first and second layer of material both including silicon. The method includes generating at least one predicted behavior curve associated with a depth profile of an interface between the first and second layer of material, the predicted behavior curve including at least one expected optical measurement, the depth profile associated with the interface being present at a particular theoretical depth. The method also includes emitting light onto a surface of the semiconductor device. The method further includes collecting at least one optical measurement from portions of the emitted light that are reflected by the semiconductor device. The method additionally includes comparing the at least one optical measurement to the predicted behavior curve and determining the approximate actual depth of the interface in response to the compared optical measurement.