摘要:
A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The top electrode, the ferroelectric layer, and the bottom electrode are patterned or etched. A dry clean is performed that mitigates edge degradation. A wet etch/clean is then performed.
摘要:
A dual damascene process flow for forming interconnect lines and vias in which at least part of the via (116) is etched prior to the trench etch. A low-k material such as a thermoset organic polymer is used for the ILD (106) and IMD (110). After the at least partial via etch, a BARC (120) is deposited over the structure including in the via (116). Then, the trench (126) is patterned and etched. Although at least some of the BARC (120) material is removed during the trench etch, the bottom of the via (116) is protected.
摘要:
A semiconductor surface measurement system (100) is disclosed. In this system, a plurality of wafers (106), each having an exposed surface, are held by a wafer positioning system (104), which sequentially moves the wafers into a measurement zone. A wafer position detection system (124) detects the position of a selected wafer, and generates an output signal indicating the position of the selected wafer. A surface measurement apparatus (114 through 121, 130 through 142) measures a property of the exposed surface of the selected wafer (106) in response to the output signal of the wafer position detection system (124) when the selected wafer is in the measurement zone. The disclosed surface measurement system (100)may be used to gather real-time data concerning surface properties such as composition, roughness and epilayer thickness during multi-wafer semiconductor processing.
摘要:
A dual damascene process for low-k or ultra low-k dielectric such as organo-silicate glass (OSG). After the via (112) etch, a trench (121) is etched in the OSG layer (108) using a less-polymerizing fluorocarbon added to an etch chemistry comprising a fluorocarbon and low N2/Ar ratio. The low N2/Ar ratio controls ridge formation during the trench etch. The combination of a less-polymerizing fluorocarbon with a higher-polymerizing fluorocarbon achieves a high etch rate and defect-free conditions.
摘要:
Molecular beam epitaxy (202) with growing layer thickness and doping control (206) by feedback of sensor signals such as spectrosceopic ellipsometer signals based on a process model. Examples include III-V compound structures with multiple AlAs, InGaAs, and InAs layers as used in resonant tunneling diodes and hetrojunction bipolar transistors with doped and undoped GaAs layers, AlGaAs and InGaAs.
摘要:
Molecular beam epitaxy (202) with growing layer thickness control (206) by feedback of integrated mass spectormeter (204) signals. Examples include III-V compound structures with multiple AlAs, InGaAs, and InAs layers as used in resonant tunneling diodes.
摘要:
Preferred embodiments mask select regions of a circuit surface (141) prior to abrading the surface with diamond particles to form nucleation sites (200). The mask (150) is then removed prior to forming a diamond layer (160). Diamond layer (160) grows on the surface except in those regions wherein the mask (150) prevented the formation of nucleation sites (200).
摘要:
A method and system for etching a substrate control selectivity of the etch process by modulating the gas specie of the reactants. The gas specie selectively form and etch a buffer layer that protects underlying etch stop materials thereby providing highly selective etch processes.
摘要:
The present invention provides a method for etching a substrate, a method for forming an integrated circuit, an integrated circuit formed using the method, and an integrated circuit. The method for etching a substrate includes, among other steps, providing a substrate 140 having an aluminum oxide etch stop layer 130 located thereunder, and then etching an opening 150, 155, in the substrate 140 using an etchant comprising carbon oxide, a fluorocarbon, an etch rate modulator, and an inert carrier gas, wherein a flow rate of the carbon oxide is greater than about 80 sccm and the etchant is selective to the aluminum oxide etch stop layer 130. The aluminum oxide etch stop layer may also be used in the back-end of advanced CMOS processes as a via etch stop layer.
摘要:
The present invention is directed to a method of forming an FeRAM integrated circuit, which includes performing a capacitor stack etch to define the FeRAM capacitor. The method comprises etching a PZT ferroelectric layer with a high temperature BCl3 etch which provides substantial selectivity with respect to the hard mask. Alternatively, the PZT ferroelectric layer is etch using a low temperature fluorine component etch chemistry such as CHF3 to provide a non-vertical PZT sidewall profile. Such a profile prevents conductive material associated with a subsequent bottom electrode layer etch from depositing on the PZT sidewall, thereby preventing leakage or a “shorting out” of the resulting FeRAM capacitor.
摘要翻译:本发明涉及形成FeRAM集成电路的方法,其包括执行电容器堆叠蚀刻以限定FeRAM电容器。 该方法包括用提供相对于硬掩模的实质选择性的高温BCl 3 N 3蚀刻来蚀刻PZT铁电层。 或者,PZT铁电层是使用诸如CHF 3 N 3的低温氟成分蚀刻化学品进行蚀刻,以提供非垂直PZT侧壁轮廓。 这种轮廓防止与随后的底部电极层蚀刻相关联的导电材料沉积在PZT侧壁上,从而防止所得FeRAM电容器的泄漏或“短路”。