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公开(公告)号：US06521042B1
公开(公告)日：2003-02-18
申请号：US08667660
申请日：1996-06-21
IPC分类号： C30B2516
CPC分类号： H01L29/882 , B82Y10/00 , B82Y15/00 , C30B23/002 , C30B29/40 , H01L21/02392 , H01L21/02463 , H01L21/02546 , H01L21/02631 , Y10T117/1004 , Y10T117/1008
摘要： Molecular beam epitaxy (202) with growing layer thickness control (206) by feedback of mass spectrometer (204) signals based on a process model. Examples include III-V compound structures with multiple AlAs, InGaAs, and InAs layers as used in resonant tunneling diodes.
摘要翻译： 基于过程模型，通过质谱仪（204）反馈信号生长层厚度控制（206）的分子束外延（202）。 实例包括具有多个AlAs，InGaAs和InAs层的III-V族化合物结构，如共振隧道二极管所用。
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公开(公告)号：US5985025A
公开(公告)日：1999-11-16
申请号：US382324
申请日：1995-02-01
IPC分类号： C30B23/08 , C30B23/02 , C30B29/68 , H01L21/203 , H01L21/338 , H01L29/812 , H01L29/88 , C30B25/16
CPC分类号： H01L29/882 , B82Y10/00 , B82Y15/00 , C30B23/002 , C30B29/40 , H01L21/02392 , H01L21/02463 , H01L21/02546 , H01L21/02631 , Y10T117/1004 , Y10T117/1008
摘要： Molecular beam epitaxy (202) with growing layer thickness control (206) by feedback of mass spectrometer (204) signals based on a process model. Examples include III-V compound structures with multiple AlAs, InGaAs, and InAs layers as used in resonant tunneling diodes.
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3.发明授权公开(公告)号：US07183602B2
公开(公告)日：2007-02-27
申请号：US11033224
申请日：2005-01-11
CPC分类号： H01L27/11507 , H01L28/57
摘要： Hydrogen barriers and fabrication methods are provided for protecting ferroelectric capacitors (CFE) from hydrogen diffusion in semiconductor devices (102), wherein nitrided aluminum oxide (N—AlOx) is formed over a ferroelectric capacitor (CFE), and one or more silicon nitride layers (112, 117) are formed over the nitrided aluminum oxide (N—AlOx). Hydrogen barriers are also provided in which an aluminum oxide (AlOx, N—AlOx) is formed over the ferroelectric capacitors (CFE), with two or more silicon nitride layers (112, 117) formed over the aluminum oxide (AlOx, N—AlOx), wherein the second silicon nitride layer (112) comprises a low silicon-hydrogen SiN material.
摘要翻译： 提供氢屏障和制造方法用于在半导体器件（102）中保护铁电电容器（C LIMIT）免受氢扩散，其中氮化的氧化铝（N-AlOx）形成在铁电电容器（C < 在氮化的氧化铝（N-AlOx）上形成一个或多个氮化硅层（112,117）。 还提供了氢屏障，其中在铁电电容器（CFE）上形成氧化铝（AlOx，N-AlOx），其上形成有两个或更多个氮化硅层（112,117） 氧化铝（AlOx，N-AlOx），其中第二氮化硅层（112）包括低硅氢SiN材料。
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4.发明授权公开(公告)号：US06686210B1
公开(公告)日：2004-02-03
申请号：US09349439
申请日：1999-07-09
IPC分类号： H01L2100
CPC分类号： H01L28/55 , C23C16/40 , C23C16/409 , C23C16/44 , C23C16/517 , H01L21/31604 , H01L21/31691 , H01L27/0629 , H01L27/0805 , H01L28/60
摘要： A method for controlling the crystallographic texture of thin films with anisotropic ferroelectric polarization or permittivity by means of ion bombardment resulting in a texture with higher ferroelectric polarization or permittivity which is normally energetically disfavored.
摘要翻译： 通过离子轰击来控制具有各向异性铁电极化或介电常数的薄膜的晶体结构的方法，导致通常在能量上不利的铁电极化或介电常数较高的纹理。
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公开(公告)号：US5905272A
公开(公告)日：1999-05-18
申请号：US960988
申请日：1997-10-30
申请人： Theodore S. Moise
发明人： Theodore S. Moise
IPC分类号： H01L27/144 , H01L31/08 , H01L29/06
CPC分类号： B82Y10/00 , H01L27/144 , H01L31/08
摘要： Apparatus for optical communications (10, 110, 210) includes a low-temperature grown photoconductor (12, 140, 220) coupled to at least one resonant tunneling device (14, 120, 130, 230, 240). When exposed to an input light, low-temperature grown photoconductor (10, 110, 210) absorbs photons, which decreases the resistivity, and thus the resistance of the photoconductor. This decrease in resistance causes a decrease in the voltage drop across photoconductor (12, 140, 220), which causes a corresponding increase in the voltage drop across resonant tunneling device (14, 120, 130, 230, 140).
摘要翻译： 用于光通信的装置（10,110,210）包括耦合到至少一个谐振隧穿装置（14,120,130,230,240）的低温生长的光电导体（12,140,220）。 当暴露于输入光时，低温生长的光电导体（10,110,210）吸收光子，这降低了电阻率，并因此降低了光电导体的电阻。 电阻的这种降低导致光电导体（12,140,220）上的电压降的降低，这导致谐振隧穿装置（14,120,130,230,140）上的电压降的相应增加。
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公开(公告)号：US5442194A
公开(公告)日：1995-08-15
申请号：US178676
申请日：1994-01-07
申请人： Theodore S. Moise
发明人： Theodore S. Moise
IPC分类号： H01L29/68 , H01L29/06 , H01L29/205 , H01L29/76 , H01L29/161 , H01L27/12 , H01L29/72
CPC分类号： H01L29/7606
摘要： A hot-electron transistor (10) is formed on substrate (12) having an outer surface. The present transistor includes subcollector layer (14) comprising Indium Gallium Arsenide formed outwardly from the outer surface of substrate (12). Collector barrier layer (18) comprising Indium Aluminum Gallium Arsenide is outwardly formed from subcollector layer (14), and collector barrier layer (18) minimizes leakage current in transistor (10). Outwardly from collector barrier layer (18) is formed base layer (20) comprising Indium Gallium Arsenide. Tunnel injector layer (21) comprising Aluminum Arsenide for ballistically transporting electrons in transistor (10) is outwardly formed from base layer (20), and emitter layer (24) comprising Indium Aluminum Arsenide is outwardly formed from tunnel injector layer (21).
摘要翻译： 在具有外表面的基板（12）上形成热电子晶体管（10）。 本晶体管包括从基板（12）的外表面向外形成的包含砷化铟镓的子集电极层（14）。 包含铟铝镓砷化物的集电极阻挡层（18）由子集电极层（14）向外形成，并且集电极势垒层（18）使晶体管（10）中的漏电流最小化。 从集电极阻挡层（18）向外形成包含砷化镓的基底层（20）。 包括用于在晶体管（10）中弹性传输电子的砷化铝的隧道喷射器层（21）由基底层（20）向外形成，并且包括砷化铝铝的发射极层（24）由隧道喷射器层（21）向外形成。
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公开(公告)号：US20090194801A1
公开(公告)日：2009-08-06
申请号：US12025207
申请日：2008-02-04
申请人： Francis Gabriel Celii , Robert Kraft , Kezhakkedath R. Udayakumar , Scott Robert Summerfelt , Theodore S. Moise
发明人： Francis Gabriel Celii , Robert Kraft , Kezhakkedath R. Udayakumar , Scott Robert Summerfelt , Theodore S. Moise
CPC分类号： H01L27/11507 , H01L28/55 , H01L28/65 , H01L28/75
摘要： A method of manufacturing a semiconductor device. The method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive residue is generated on sidewalls of the ferroelectric capacitor as a by-product of the patterning. The method also comprises removing the conductive residue using a physical plasma etch clean-up process that includes maintaining a substrate temperature that is greater than about 60° C.
摘要翻译： 一种制造半导体器件的方法。 该方法包括在半导体衬底上形成导电和铁电材料层。 图案化材料层以形成铁电电容器的铁电层，其中作为图案化的副产品，在铁电电容器的侧壁上产生导电残留物。 该方法还包括使用包括保持大于约60℃的衬底温度的物理等离子体蚀刻清理工艺去除导电残留物。
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8.发明授权公开(公告)号：US06982448B2
公开(公告)日：2006-01-03
申请号：US10803445
申请日：2004-03-18
CPC分类号： H01L27/11507 , H01L28/57
摘要： Hydrogen barriers and fabrication methods are provided for protecting ferroelectric capacitors (CFE) from hydrogen diffusion in semiconductor devices (102), wherein nitrided aluminum oxide (N—AlOx) is formed over a ferroelectric capacitor (CFE), and one or more silicon nitride layers (112, 117) are formed over the nitrided aluminum oxide (N—AlOx). Hydrogen barriers are also provided in which an aluminum oxide (AlOx, N—AlOx) is formed over the ferroelectric capacitors (CFE), with two or more silicon nitride layers (112, 117) formed over the aluminum oxide (AlOx, N—AlOx), wherein the second silicon nitride layer (112) comprises a low silicon-hydrogen SiN material.
摘要翻译： 提供了氢屏障和制造方法，用于保护铁电电容器（CFE）在半导体器件（102）中的氢扩散，其中氮化的氧化铝（N-AlO x X）为 形成在铁电电容器（CFE）上，并且在氮化的氧化铝（N-AlO x N）上形成一个或多个氮化硅层（112,117）。 还提供了氢屏障，其中在铁电电容器（C FE）上形成氧化铝（AlO x N，N-AlO x x） ，其上形成有氧化铝（AlO x N，N-AlO x）上的两个或更多个氮化硅层（112,117），其中第二氮化硅层（112 ）包括低硅氢SiN材料。
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公开(公告)号：US06211035B1
公开(公告)日：2001-04-03
申请号：US09392988
申请日：1999-09-09
申请人： Theodore S. Moise , Guoqiang Xing , Mark Visokay , Justin F. Gaynor , Stephen R. Gilbert , Francis Celii , Scott R. Summerfelt , Luigi Colombo
发明人： Theodore S. Moise , Guoqiang Xing , Mark Visokay , Justin F. Gaynor , Stephen R. Gilbert , Francis Celii , Scott R. Summerfelt , Luigi Colombo
IPC分类号： H01L2120
CPC分类号： H01L27/11502 , H01L21/0332 , H01L21/31116 , H01L21/31144 , H01L27/10852 , H01L27/11507 , H01L28/55
摘要： A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.
摘要翻译： 在电极之间与电介质之间的电介质与绝缘扩散阻挡层之间的电介质接触电容器的通孔蚀刻包括基于F的电介质蚀刻和基于Cl和F的势垒蚀刻的两步蚀刻。
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10.发明授权Sputtering process for the conformal deposition of a metallization or insulating layer 失效用于金属化或绝缘层的共形沉积的溅射工艺
公开(公告)号：US6100200A
公开(公告)日：2000-08-08
申请号：US218563
申请日：1998-12-21
申请人： Peter C. Van Buskirk , Michael W. Russell , Daniel J. Vestyck , Scott R. Summerfelt , Theodore S. Moise
发明人： Peter C. Van Buskirk , Michael W. Russell , Daniel J. Vestyck , Scott R. Summerfelt , Theodore S. Moise
IPC分类号： C23C14/04 , C23C14/34 , H01L21/02 , H01L21/285 , H01L21/768 , H01L21/311
CPC分类号： H01L28/55 , C23C14/046 , C23C14/34 , H01L21/76877 , H01L21/76895 , H01L21/2855
摘要： The present invention is a method related to the deposition of a metallization layer in a trench in a semiconductor substrate. The focus of the invention is to sequentially perform heated deposition and etch unit processes to provide a good conformal film of metal on the inner surfaces of a via or trench. The deposition and etch steps can also be performed simultaneously.
摘要翻译： 本发明是涉及在半导体衬底中的沟槽中沉积金属化层的方法。 本发明的重点是依次执行加热沉积和蚀刻单元工艺以在通孔或沟槽的内表面上提供良好的金属保形膜。 沉积和蚀刻步骤也可以同时进行。
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