公开(公告)号：US09224644B2

公开(公告)日：2015-12-29

申请号：US13726972

申请日：2012-12-26

Applicant: Intermolecular, Inc.

Inventor： Sandip Niyogi ,  Amol Joshi ,  Chi-I Lang ,  Salil Mujumdar

IPC: H01L21/768 ,  C23C14/58 ,  C23C16/455 ,  H01L21/02 ,  H01L21/3115 ,  H01L21/3215 ,  H01J37/32 ,  H01L21/28 ,  H01L29/51 ,  H01L21/67 ,  H01L21/687 ,  H01L29/66

CPC classification number: H01L21/76886 ,  C23C14/5826 ,  C23C16/45536 ,  H01J37/32357 ,  H01L21/02181 ,  H01L21/022 ,  H01L21/02323 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/31155 ,  H01L21/3215 ,  H01L21/67207 ,  H01L21/68764 ,  H01L21/68792 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653

Abstract: Methods and apparatus for processing using a remote plasma source are disclosed. The apparatus includes an outer chamber enclosing a substrate support, a remote plasma source, and a showerhead. A substrate heater can be mounted in the substrate support. A transport system moves the substrate support and is capable of positioning the substrate. The remote plasma source may be used to provide a plasma surface treatment or as a source to incorporate dopants into a pre-deposited layer.

Abstract translation: 公开了使用远程等离子体源的处理方法和装置。 该装置包括封闭衬底支撑件，远程等离子体源和喷头的外室。 基板加热器可以安装在基板支撑件中。 运输系统移动基板支撑件并且能够定位基板。 远程等离子体源可用于提供等离子体表面处理或作为将掺杂剂掺入预沉积层的源。

公开(公告)号：US20150093889A1

公开(公告)日：2015-04-02

申请号：US14044376

申请日：2013-10-02

Applicant: Intermolecular ,  GLOBALFOUNDRIES, Inc.

Inventor： Bin Yang ,  Abhijit Pethe ,  Albert Lee ,  Amol Joshi ,  Ashish Bodke ,  Kevin Kashefi ,  Salil Mujumdar

IPC: H01L29/51

CPC classification number: H01L29/517 ,  H01L21/28255 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659

Abstract: Methods for fabricating integrated circuits are provided in various exemplary embodiments. In one embodiment, a method for fabricating an integrated circuit includes providing a germanium-based semiconductor substrate comprising a GeOx layer formed thereon having a first thickness, removing a portion of the GeOx layer by exposing the semiconductor substrate to a hydrogen-plasma dry etch so as to reduce the first thickness of the GeOx layer to a second thickness, and depositing a high-k material over the GeOx layer of the semiconductor substrate.

Abstract translation: 在各种示例性实施例中提供了用于制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括：提供锗基半导体衬底，其包含在其上形成的具有第一厚度的GeO x层，通过将半导体衬底暴露于氢等离子体干法蚀刻来去除GeOx层的一部分，从而 以将GeOx层的第一厚度减小到第二厚度，以及在半导体衬底的GeO x层上沉积高k材料。

公开(公告)号：US09362283B2

公开(公告)日：2016-06-07

申请号：US14793005

申请日：2015-07-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhendong Hong ,  Susie Tzeng ,  Amol Joshi ,  Ashish Bodke ,  Divya Pisharoty ,  Usha Raghuram ,  Olov Karlsson ,  Kisik Choi ,  Salil Mujumdar ,  Paul R. Besser ,  Jinping Liu ,  Hoon Kim

IPC: H01L27/00 ,  H01L29/00 ,  H01L27/092 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/49

CPC classification number: H01L27/0922 ,  H01L21/28097 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823835 ,  H01L27/092 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545

Abstract: An integrated circuit product includes an NMOS transistor having a gate structure that includes an NMOS gate insulation layer, a first NMOS metal layer positioned on the NMOS gate insulation layer, an NMOS metal silicide material positioned above the first NMOS metal layer, and a layer of a second metal material positioned above and in contact with the NMOS gate insulation layer, the first NMOS metal layer, and the NMOS metal silicide layer. The PMOS transistor has a gate structure that includes a PMOS gate insulation layer, a first PMOS metal layer positioned on the PMOS gate insulation layer, a PMOS metal silicide material positioned above the first PMOS metal layer, and a layer of the second metal material positioned above and in contact with the PMOS gate insulation layer, the first PMOS metal layer, and the PMOS metal silicide layer.

Abstract translation: 集成电路产品包括具有栅极结构的NMOS晶体管，该栅极结构包括NMOS栅绝缘层，位于NMOS栅绝缘层上的第一NMOS金属层，位于第一NMOS金属层上方的NMOS金属硅化物材料， 位于NMOS栅极绝缘层上方并与NMOS栅绝缘层接触的第二金属材料，第一NMOS金属层和NMOS金属硅化物层。 PMOS晶体管具有栅极结构，其包括PMOS栅极绝缘层，位于PMOS栅极绝缘层上的第一PMOS金属层，位于第一PMOS金属层上方的PMOS金属硅化物材料和位于第一PMOS金属层上方的第二金属材料层 并且与PMOS栅绝缘层，第一PMOS金属层和PMOS金属硅化物层接触。

公开(公告)号：US20150093914A1

公开(公告)日：2015-04-02

申请号：US14044514

申请日：2013-10-02

Applicant: Intermolecular ,  GLOBALFOUNDRIES, Inc.

Inventor： Bin Yang ,  Abhijit Pethe ,  Albert Lee ,  Amol Joshi ,  Ashish Bodke ,  Kevin Kashefi ,  Salil Mujumdar

IPC: H01L21/02

CPC classification number: H01L21/02178 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/2807 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: Methods for fabricating integrated circuits are provided in various exemplary embodiments. In one embodiment, a method for fabricating an integrated circuit includes providing a germanium-based semiconductor substrate comprising a GeOx layer formed thereon and exposing the semiconductor substrate to first and second atomic layer deposition (ALD) processes. The first ALD process includes exposing the semiconductor substrate to a first gaseous precursor comprising aluminum and exposing the semiconductor substrate to a second gaseous precursor comprising a first oxygen-containing precursor. The second ALD process includes exposing the semiconductor substrate to a first gaseous precursor comprising aluminum and exposing the semiconductor substrate to a second gaseous precursor comprising a second oxygen-containing precursor.

Abstract translation: 在各种示例性实施例中提供了用于制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括提供包括形成在其上的GeO x层的锗基半导体衬底，并将半导体衬底暴露于第一和第二原子层沉积（ALD）工艺。 第一ALD工艺包括将半导体衬底暴露于包含铝的第一气态前体，并将半导体衬底暴露于包含第一含氧前体的第二气态前体。 第二ALD工艺包括将半导体衬底暴露于包含铝的第一气态前体，并将半导体衬底暴露于包含第二含氧前体的第二气态前体。

公开(公告)号：US20150093887A1

公开(公告)日：2015-04-02

申请号：US14253668

申请日：2014-04-15

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Bin Yang ,  Shurong Liang ,  Kristina Young-Fisher ,  Kevin Kashefi ,  Amol Joshi ,  Salil Mujumdar ,  Abhijit Pethe ,  Albert Lee ,  Ashish Bodke

IPC: H01L21/3065 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L21/28255 ,  H01L21/02046 ,  H01L21/2807 ,  H01L21/31116 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: Methods for fabricating integrated circuits are provided in various exemplary embodiments. In one embodiment, a method for fabricating an integrated circuit includes providing a germanium-based semiconductor substrate including a GeOx layer formed thereon having a first thickness, removing a portion of the GeOx layer by exposing the semiconductor substrate to a NF3/NH3 plasma dry etch so as to reduce the first thickness of the GeOx layer to a second thickness, and depositing a high-k material over the GeOx layer of the semiconductor substrate.

Abstract translation: 在各种示例性实施例中提供了用于制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括提供锗基半导体衬底，其包括在其上形成的具有第一厚度的GeO x层，通过将半导体衬底暴露于NF3 / NH3等离子体干蚀刻来去除GeOx层的一部分 以便将GeO x层的第一厚度减小到第二厚度，并且在半导体衬底的GeO x层上沉积高k材料。

公开(公告)号：US20150061027A1

公开(公告)日：2015-03-05

申请号：US14017485

申请日：2013-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhendong Hong ,  Susie Tzeng ,  Amol Joshi ,  Ashish Bodke ,  Divya Pisharoty ,  Usha Raghuram ,  Olov Karlsson ,  Kisik Choi ,  Salil Mujumdar ,  Paul R. Besser ,  Jinping Liu ,  Hoon Kim

IPC: H01L27/092 ,  H01L21/28

CPC classification number: H01L27/0922 ,  H01L21/28097 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823835 ,  H01L27/092 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545

Abstract: One method for forming replacement gate structures for NMOS and PMOS transistors includes performing an etching process to remove a sacrificial gate structure for the NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, depositing a gate insulation layer in the gate cavities, depositing a first metal layer on the gate insulation layer in the gate cavities, performing at least one process operation to form (1) an NMOS metal silicide material above the first metal layer within the NMOS gate cavity, the NMOS metal silicide material having a first amount of atomic silicon, and (2) a PMOS metal silicide material above the first metal layer within the PMOS gate cavity, the PMOS metal silicide material having a second amount of atomic silicon, and wherein the first and second amounts of atomic silicon are different, and forming gate cap layers within the NMOS and PMOS gate cavities.

Abstract translation: 用于形成用于NMOS和PMOS晶体管的替代栅极结构的一种方法包括执行蚀刻工艺以去除用于NMOS和PMOS晶体管的牺牲栅极结构，由此限定NMOS和PMOS栅极腔，在栅极腔中沉积栅极绝缘层， 在栅极腔中的栅极绝缘层上的第一金属层，执行至少一个处理操作以在NMOS栅极腔内的第一金属层上方形成（1）NMOS金属硅化物材料，所述NMOS金属硅化物材料具有第一量 原子硅，和（2）在PMOS栅极腔内的第一金属层上方的PMOS金属硅化物材料，PMOS金属硅化物材料具有第二量的原子硅，并且其中第一和第二量的原子硅是不同的，以及 在NMOS和PMOS门腔内形成栅极盖层。

公开(公告)号：US09105497B2

公开(公告)日：2015-08-11

申请号：US14017485

申请日：2013-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhendong Hong ,  Susie Tzeng ,  Amol Joshi ,  Ashish Bodke ,  Divya Pisharoty ,  Usha Raghuram ,  Olov Karlsson ,  Kisik Choi ,  Salil Mujumdar ,  Paul R. Besser ,  Jinping Liu ,  Hoon Kim

IPC: H01L21/28 ,  H01L27/092 ,  H01L29/51 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L21/28097 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823835 ,  H01L27/092 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545

Abstract: One method for forming replacement gate structures for NMOS and PMOS transistors includes performing an etching process to remove a sacrificial gate structure for the NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, depositing a gate insulation layer in the gate cavities, depositing a first metal layer on the gate insulation layer in the gate cavities, performing at least one process operation to form (1) an NMOS metal silicide material above the first metal layer within the NMOS gate cavity, the NMOS metal silicide material having a first amount of atomic silicon, and (2) a PMOS metal silicide material above the first metal layer within the PMOS gate cavity, the PMOS metal silicide material having a second amount of atomic silicon, and wherein the first and second amounts of atomic silicon are different, and forming gate cap layers within the NMOS and PMOS gate cavities.

Abstract translation: 用于形成用于NMOS和PMOS晶体管的替代栅极结构的一种方法包括执行蚀刻工艺以去除用于NMOS和PMOS晶体管的牺牲栅极结构，由此限定NMOS和PMOS栅极腔，在栅极腔中沉积栅极绝缘层， 在栅极腔中的栅极绝缘层上的第一金属层，执行至少一个处理操作以在NMOS栅极腔内的第一金属层上方形成（1）NMOS金属硅化物材料，所述NMOS金属硅化物材料具有第一量 原子硅，和（2）在PMOS栅极腔内的第一金属层上方的PMOS金属硅化物材料，PMOS金属硅化物材料具有第二量的原子硅，并且其中第一和第二量的原子硅是不同的，以及 在NMOS和PMOS门腔内形成栅极盖层。