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    Devices and methods of forming low resistivity noble metal interconnect
    11.
    发明授权
    Devices and methods of forming low resistivity noble metal interconnect 有权

    公开(公告)号：US10679937B2

    公开(公告)日：2020-06-09

    申请号：US15785665

    申请日：2017-10-17

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Xunyuan Zhang ,  Frank W. Mont ,  Errol Todd Ryan

    IPC: H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/285 ,  H01L21/768 ,  H01L23/528

    Abstract: Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a barrier layer along a top surface of the semiconductor interconnect device; depositing and annealing a metal interconnect material over a top surface of the barrier layer, wherein the metal interconnect material fills the set of trenches and the set of vias; planarizing a top surface of the intermediate semiconductor interconnect device; exposing a portion of the barrier layer between the set of trenches and the set of vias; and depositing a dielectric cap. Also disclosed is an intermediate device formed by the method.

    METHODS OF PROTECTING STRUCTURE OF INTEGRATED CIRCUIT FROM REWORK
    12.
    发明申请
    METHODS OF PROTECTING STRUCTURE OF INTEGRATED CIRCUIT FROM REWORK 审中-公开

    公开(公告)号：US20190318927A1

    公开(公告)日：2019-10-17

    申请号：US15954066

    申请日：2018-04-16

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Lei Sun ,  Xunyuan Zhang ,  Frank W. Mont ,  Shao Beng Law

    IPC: H01L21/033 ,  H01L21/768 ,  H01L21/027 ,  H01L21/02

    Abstract: The present disclosure relates to methods of protecting a structure of an integrated circuit (IC) from rework, and more particularly, to methods of protecting a structure of an IC without impacting the critical dimension or the profile of the structure. For example, a method of protecting a structure of an IC from rework may include forming a first layer on a second layer; forming one or more first openings in the first layer, the first openings exposing a top surface of the second layer; selectively growing a Group VIII metal within the one or more first openings, thereby forming one or more first plugs; forming one or more final openings in the first layer; and removing the one or more first plugs.

    Forming interconnect features with reduced sidewall tapering
    15.
    发明授权
    Forming interconnect features with reduced sidewall tapering 有权
    形成互连功能，减少侧壁渐缩

    公开(公告)号：US09373543B1

    公开(公告)日：2016-06-21

    申请号：US14876023

    申请日：2015-10-06

    Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

    Inventor： Frank W. Mont ,  Shariq Siddiqui ,  Douglas M. Trickett ,  Brown Cornelius Peethala

    IPC: H01L21/4763 ,  H01L21/768 ,  H01L21/311

    CPC classification number: H01L21/76808 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76897

    Abstract: A method includes forming a stack of materials including a first dielectric layer having a conductive feature positioned therein, and a second dielectric layer positioned above the first dielectric layer. An etch mask including a plurality of spaced apart mask elements is formed above the second dielectric layer. The mask elements define at least a first via opening exposing the second dielectric layer. A patterning layer is formed above the etch mask. A second via opening is formed in the patterning layer to expose the first via opening in the etch mask. The second dielectric layer is etched through the second via opening to define a third via opening in the second dielectric layer exposing the conductive feature. The patterning layer and the etch mask are removed. A conductive via contacting the conductive feature is formed in the third via opening.

    Abstract translation: 一种方法包括形成包括其中定位有导电特征的第一介电层的材料堆叠和位于第一介电层上方的第二介电层。 包括多个间隔开的掩模元件的蚀刻掩模形成在第二介电层的上方。 掩模元件至少限定了暴露第二介电层的第一通孔。 在蚀刻掩模上方形成图形层。 在图案化层中形成第二通孔，以露出蚀刻掩模中的第一通孔。 通过第二通孔开口蚀刻第二电介质层，以在暴露导电特征的第二电介质层中限定第三通孔。 图案化层和蚀刻掩模被去除。 在第三通孔中形成有与导电特征接触的导电通路。

    Skip via structures
    17.
    发明授权
    Skip via structures 有权

    公开(公告)号：US10262892B2

    公开(公告)日：2019-04-16

    申请号：US15345882

    申请日：2016-11-08

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Xunyuan Zhang ,  Frank W. Mont ,  Errol Todd Ryan

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to skip via structures and methods of manufacture. The structure includes: a first wiring layer with one or more wiring structures; a second wiring layer with one or more wiring structures, located above the first wiring layer; a skip via with metallization, which passes through upper wiring levels including the second wiring layer and which makes contact with the one or more wiring structures of the first wiring layer; and a via structure which comprises a protective material and contacts at least one of the one or more wiring structures at the upper wiring level.

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