公开(公告)号：US20160020204A1

公开(公告)日：2016-01-21

申请号：US14871181

申请日：2015-09-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar SINGH ,  Andy WEI ,  Mahadeva Iyer NATARAJAN

IPC: H01L27/02 ,  H01L29/45 ,  H01L29/417 ,  H01L29/06

CPC classification number: H01L29/0657 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3086 ,  H01L27/0251 ,  H01L27/0255 ,  H01L27/0259 ,  H01L27/0296 ,  H01L29/41708 ,  H01L29/456 ,  H01L29/861 ,  H01L29/866

Abstract: Three-dimensional electrostatic discharge (ESD) semiconductor devices are fabricated together with three-dimensional non-ESD semiconductor devices. For example, an ESD diode and FinFET are fabricated on the same bulk semiconductor substrate. A spacer merger technique is used in the ESD portion of a substrate to create double-width fins on which the ESD devices can be made larger to handle more current.

公开(公告)号：US20150236133A1

公开(公告)日：2015-08-20

申请号：US14181790

申请日：2014-02-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar SINGH ,  Andy WEI ,  Gopal SRINIVASAN ,  Amaury GENDRON

IPC: H01L29/66 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/306 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L29/66795 ,  H01L21/3086 ,  H01L27/0629 ,  H01L29/785 ,  H01L29/94

Abstract: Devices and methods for forming semiconductor devices with wider FinFETs for higher tunability of the varactor are provided. One method includes, for instance: obtaining an intermediate semiconductor device; applying a spacer layer over the semiconductor device; etching the semiconductor device to remove at least a portion of the spacer layer to expose the plurality of mandrels; removing the mandrels; etching the semiconductor device to remove a portion of the dielectric layer; forming at least one fin; and removing the spacer layer and the dielectric layer. One intermediate semiconductor device includes, for instance: a substrate; a dielectric layer over the substrate; a plurality of mandrels formed on the dielectric layer, the mandrels including a first set of mandrels and a second set of mandrels, wherein the first set of mandrels have a width twice as large as the second set of mandrels; and a spacer layer applied over the mandrels.

Abstract translation: 提供了用于形成具有更宽FinFET的半导体器件以用于变容二极管的较高可调性的装置和方法。 一种方法包括，例如：获得中间半导体器件; 在所述半导体器件上施加间隔层; 蚀刻半导体器件以去除间隔层的至少一部分以暴露多个心轴; 去除心轴; 蚀刻半导体器件以去除电介质层的一部分; 形成至少一个翅片; 以及去除间隔层和电介质层。 一个中间半导体器件包括例如：衬底; 介电层; 形成在所述电介质层上的多个心轴，所述心轴包括第一组心轴和第二组心轴，其中所述第一组心轴的宽度是所述第二组心轴的两倍; 以及施加在心轴上的间隔层。

公开(公告)号：US20180175179A1

公开(公告)日：2018-06-21

申请号：US15897820

申请日：2018-02-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Biswanath SENAPATI ,  Jagar SINGH

IPC: H01L29/735 ,  H01L29/423 ,  H01L29/417 ,  H01L29/10 ,  H01L29/08 ,  G01R31/26 ,  H01L29/06 ,  H01L27/06 ,  H01L27/02 ,  H01L21/66 ,  G01R31/28

CPC classification number: H01L29/735 ,  G01R31/2621 ,  G01R31/2884 ,  H01L22/34 ,  H01L27/0259 ,  H01L27/0623 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/1095 ,  H01L29/41708 ,  H01L29/42304

Abstract: A symmetrical lateral bipolar junction transistor (SLBJT) is provided. The SLBJT includes a p-type semiconductor substrate, a n-type well, an emitter of a SLBJT situated in the n-type well, a base of the SLBJT situated in the n-type well and spaced from the emitter by a distance on one side of the base, a collector of the SLBJT situated in the n-type well and spaced from the base by the distance on an opposite side of the base, and an electrical connection to the substrate outside the n-type well. The SLBJT is used to characterize a transistor in a circuit by electrically coupling the SLBJT to a gate of the test transistor, applying a voltage to the gate, and characterizing aspect(s) of the test transistor under the applied voltage. The SLBJT protects the gate against damage to the gate dielectric.

公开(公告)号：US20180026113A1

公开(公告)日：2018-01-25

申请号：US15616653

申请日：2017-06-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar SINGH

IPC: H01L29/66 ,  H01L27/08 ,  H01L29/06 ,  H01L21/762 ,  H01L29/861 ,  H01L21/265

CPC classification number: H01L21/76224 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/861 ,  H01L29/872

Abstract: Methods for forming a fin-based RF diode with improved performance characteristics and the resulting devices are disclosed. Embodiments include forming fins over a substrate, separated from each other, each fin having a lower portion and an upper portion; forming STI regions over the substrate, between the lower portions of adjacent fins; implanting the lower portion of each fin with a first-type dopant; implanting the upper portion of each fin, above the STI region, with the first-type dopant; forming a junction region around a depletion region and along exposed sidewalls and a top surface of the upper portion of each fin; and forming a contact on exposed sidewalls and a top surface of each junction region.

公开(公告)号：US20170338180A1

公开(公告)日：2017-11-23

申请号：US15157582

申请日：2016-05-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Scott BEASOR ,  Jagar SINGH

IPC: H01L23/525 ,  H01L27/06 ,  H01L23/522 ,  H01L21/8234 ,  H01L23/34 ,  H01L29/45 ,  H01L23/528

CPC classification number: H01L23/5256 ,  H01L21/823475 ,  H01L23/3677 ,  H01L27/0629

Abstract: A method for producing semiconductor devices including an electrical fuse (e-fuse) and the resulting device are provided. Embodiments include forming a gate electrode (PC); forming at least one gate contact (CB) over the PC; forming at least one source/drain contact (CA); and forming an e-fuse including a resistor metal (RM) between at least one CB and an equal number of CAs to dissipate heat generated by the PC.

公开(公告)号：US20160064371A1

公开(公告)日：2016-03-03

申请号：US14471712

申请日：2014-08-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jian-Hsing LEE ,  Jagar SINGH ,  Manjunatha PRABHU ,  Anil KUMAR ,  Mahadeva Iyer NATARAJAN ,  Min-hwa CHI

IPC: H01L27/02 ,  H01L21/8249 ,  H01L27/06

CPC classification number: H01L27/0259

Abstract: Protecting non-planar output transistors from electrostatic discharge (ESD) events includes providing a non-planar semiconductor structure, the structure including a semiconductor substrate with a well of n-type or p-type. The provided non-planar structure further includes raised semiconductor structure(s) coupled to the substrate, non-planar transistor(s) of a type opposite the well, each transistor being situated on one of the raised structure(s), the non-planar transistor(s) each including a source, a drain and a gate, the non-planar structure further including parasitic bipolar junction transistor(s) (BJT(s)) on the raised structure(s), each BJT including a collector and an emitter situated on the raised structure and a base being the well, and a well contact for the base of the BJT. Protecting the non-planar output transistors further includes electrically coupling the drain of the non-planar transistor and the collector of the BJT to an output of a circuit, and electrically coupling the source of the non-planar transistor, the emitter of the BJT and the well contact to a ground of the circuit.

Abstract translation: 保护非平面输出晶体管免受静电放电（ESD）事件包括提供非平面半导体结构，该结构包括具有n型或p型阱的半导体衬底。 提供的非平面结构还包括耦合到衬底的凸起的半导体结构，与阱相对的类型的非平面晶体管，每个晶体管位于凸起结构中的一个上， 每个包括源极，漏极和栅极的平面晶体管，非平面结构还包括在凸起结构上的寄生双极结晶体管（BJT（s）），每个BJT包括集电极和 位于凸起结构上的发射器和作为阱的基座，以及用于BJT的基座的阱接触。 保护非平面输出晶体管还包括将非平面晶体管的漏极和BJT的集电极电耦合到电路的输出，并且将非平面晶体管的源极，BJT的发射极和 接触到电路的地面。

公开(公告)号：US20160027905A1

公开(公告)日：2016-01-28

申请号：US14339505

申请日：2014-07-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar SINGH

IPC: H01L29/739 ,  H01L29/66 ,  H01L29/45

CPC classification number: H01L29/66325 ,  H01L29/0692 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/402 ,  H01L29/41708 ,  H01L29/45 ,  H01L29/6625 ,  H01L29/735 ,  H01L29/7393

Abstract: A structure, including a bipolar junction transistor and method of fabrication thereof, is provided herein. The bipolar junction transistor includes: a substrate including a substrate region having a first conductivity type; an emitter region over a first portion of the substrate region, the emitter region having a second conductivity type; a collector region over a second portion of the substrate region, the collector region having the second conductivity type; and, a base region overlie structure disposed over, in part, the substrate region. The base region overlie structure separates the emitter region from the collector region and aligns to a base region of the bipolar junction transistor within the substrate region, between the first portion and the second portion of the substrate region.

Abstract translation: 本文提供了一种包括双极结型晶体管及其制造方法的结构。 双极结型晶体管包括：包括具有第一导电类型的衬底区域的衬底; 在所述衬底区域的第一部分上方的发射极区域，所述发射极区域具有第二导电类型; 位于所述衬底区域的第二部分上方的集电极区域，所述集电极区域具有所述第二导电类型; 以及设置在所述衬底区域的一部分上的基底区域叠层结构。 基极区叠层结构将发射极区域与集电极区分开，并且在衬底区域内的衬底区域的第一部分和第二部分之间与双极结型晶体管的基极区域对准。

公开(公告)号：US20160020277A1

公开(公告)日：2016-01-21

申请号：US14871289

申请日：2015-09-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jagar SINGH ,  Andy WEI ,  Mahadeva Iyer NATARAJAN

IPC: H01L29/06 ,  H01L21/306 ,  H01L21/308 ,  H01L27/02

CPC classification number: H01L29/0657 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3086 ,  H01L27/0251 ,  H01L27/0255 ,  H01L27/0259 ,  H01L27/0296 ,  H01L29/41708 ,  H01L29/456 ,  H01L29/861 ,  H01L29/866

Abstract: Three-dimensional electrostatic discharge (ESD) semiconductor devices are fabricated together with three-dimensional non-ESD semiconductor devices. For example, an ESD diode and FinFET are fabricated on the same bulk semiconductor substrate. A spacer merger technique is used in the ESD portion of a substrate to create double-width fins on which the ESD devices can be made larger to handle more current.

公开(公告)号：US20210066450A1

公开(公告)日：2021-03-04

申请号：US17097425

申请日：2020-11-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jagar SINGH ,  Shiv Kumar MISHRA

IPC: H01L29/06 ,  H01L27/06 ,  H01L29/872

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high voltage diode structures and methods of manufacture. The structure includes: a diode structure composed of first well of a first dopant type in a substrate; and a well ring structure of the first dopant type in the substrate which completely surrounds the first well of the first dopant type, and spaced a distance “x” from the first well to cut a leakage path to a shallower second well of a second dopant type.

公开(公告)号：US20170141031A1

公开(公告)日：2017-05-18

申请号：US15421698

申请日：2017-02-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chun Yu WONG ,  Jagar SINGH ,  Ashish BARASKAR ,  Min-hwa CHI

IPC: H01L23/525 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L23/5256 ,  H01L21/0226 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/283 ,  H01L21/3205 ,  H01L27/11206 ,  H01L29/0673 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor fuses with nanowire fuse links and fabrication methods thereof are presented. The methods include, for instance: fabricating a semiconductor fuse, the semiconductor fuse including at least one nanowire fuse link, and the fabricating including: forming at least one nanowire, the at least one nanowire including a semiconductor material; and reacting the at least one nanowire with a metal to form the at least one nanowire fuse link of the semiconductor fuse, the at least one nanowire fuse link including a semiconductor-metal alloy. In another aspect, a structure is presented. The structure includes: a semiconductor fuse, the semiconductor fuse including: at least one nanowire fuse link, the at least one nanowire fuse link including a semiconductor-metal alloy.