公开(公告)号：US09397203B2

公开(公告)日：2016-07-19

申请号：US14677460

申请日：2015-04-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： John Z. Colt, Jr. ,  John J. Ellis-Monaghan ,  Leah M. Pastel ,  Steven M. Shank

IPC: H01L29/66 ,  H01L29/737 ,  H01L29/735 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/73

CPC classification number: H01L29/737 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/66242 ,  H01L29/6625 ,  H01L29/66265 ,  H01L29/7317 ,  H01L29/735

Abstract: Device structures, fabrication methods, and design structures for a bipolar junction transistor. A first terminal of the bipolar junction transistor is formed from a section of a device layer of a semiconductor-on-insulator wafer. An intrinsic base of the bipolar junction transistor is formed from an epitaxially-grown section of a first semiconductor layer, which is coextensive with a sidewall of the section of the device layer. A second terminal of the bipolar junction transistor is formed from a second semiconductor layer that is coextensive with the epitaxially-grown section of the first semiconductor layer. The epitaxially-grown section of a first semiconductor layer defines a first junction with the section of the device layer, and the second semiconductor layer defines a second junction with the epitaxially-grown section of the first semiconductor layer.

公开(公告)号：US20210074577A1

公开(公告)日：2021-03-11

申请号：US17086925

申请日：2020-11-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  Ian McCallum-Cook ,  Siva P. Adusumilli

IPC: H01L21/763 ,  H01L29/06 ,  H01L27/12 ,  H01L21/762 ,  H01L21/324 ,  H01L21/84 ,  H01L21/265 ,  H01L21/74 ,  H01L29/32

Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.

公开(公告)号：US10903316B2

公开(公告)日：2021-01-26

申请号：US16575675

申请日：2019-09-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  Siva P. Adusumilli

IPC: H01L21/764 ,  H01L29/06 ,  H01L23/66 ,  H01L29/10 ,  H01L29/78 ,  H01L21/762

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to radio frequency (RF) switches with airgap structures and methods of manufacture. The structure includes a substrate with at least one airgap structure formed in a well region under at least one gate structure, and which extends to a junction formed by a source/drain region of the at least one gate structure.

公开(公告)号：US10795082B1

公开(公告)日：2020-10-06

申请号：US16540452

申请日：2019-08-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Yusheng Bian ,  Theodore Letavic ,  Kenneth J. Giewont ,  Steven M. Shank

IPC: G02B6/124 ,  G02B6/12 ,  G02B6/13

Abstract: Structures that include a Bragg grating and methods of fabricating a structure that includes a Bragg grating. Bragg elements are positioned adjacent to a waveguide. The Bragg elements are separated by grooves that alternate with the Bragg elements. A dielectric layer includes portions positioned to close the grooves to define airgaps. The airgaps are respectively arranged between adjacent pairs of the Bragg elements. The Bragg elements may be used to form the Bragg grating.

公开(公告)号：US20190287847A1

公开(公告)日：2019-09-19

申请号：US15924444

申请日：2018-03-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Siva P. Adusumilli ,  Steven M. Shank

IPC: H01L21/762 ,  H01L21/768 ,  H01L23/48

Abstract: Structures with a cavity beneath semiconductor devices and methods associated with forming such substrates. A first semiconductor layer is formed on a first side of a first handle wafer. A device structure is formed that is arranged at least in part in the first semiconductor layer. After forming the device structure, the first handle wafer is thinned from a second side of the first handle wafer opposite to the first side of the first handle wafer in order to form a second semiconductor layer from the first handle wafer. After thinning the first handle wafer, a cavity is formed in the second semiconductor layer. The cavity is arranged in the second semiconductor layer beneath the device structure. A second handle wafer is attached to the second semiconductor layer to close the cavity.

公开(公告)号：US10340352B2

公开(公告)日：2019-07-02

申请号：US15458482

申请日：2017-03-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Alvin J. Joseph ,  John J. Ellis-Monaghan

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/49 ,  H01L21/311 ,  H01L21/28 ,  H01L21/265 ,  H01L21/768 ,  H01L21/84 ,  H01L23/48 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

Abstract: Device structures for a field-effect transistor and methods for forming a device structure for a field-effect transistor. A first dielectric layer is formed, and a second dielectric layer are formed on the first dielectric layer. An opening is formed that extends vertically through the first and second dielectric layers. After the first opening is formed, the second dielectric layer is laterally recessed relative to the first dielectric layer with a selective etching process, which widens a portion of the opening extending vertically through the second dielectric layer relative to a portion of the opening extending vertically through the first dielectric layer. After the second dielectric layer is laterally recessed, a gate electrode is formed that includes a narrow section in the portion of the opening extending vertically through the first dielectric layer and a wide section in the portion of the opening extending vertically through the second dielectric layer.

公开(公告)号：US20190172846A1

公开(公告)日：2019-06-06

申请号：US16258714

申请日：2019-01-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Steven M. Shank ,  Siva P. Adusumilli

IPC: H01L27/12 ,  H01L49/02 ,  H01L21/762 ,  H01L29/06 ,  H01L27/06 ,  H01L29/45 ,  H01L29/08 ,  H01L21/265 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/02

Abstract: Disclosed is an integrated circuit (IC) formation method, wherein trenches are formed within a semiconductor layer to define semiconductor mesa(s). Instead of immediately filling the trenches with an isolation material and performing a planarizing process to complete the STI regions prior to device formation, the method initially only form sidewall spacers within the trenches on the exposed sidewalls of the semiconductor mesa(s). After the sidewall spacers are formed, device(s) (e.g., field effect transistor(s), silicon resistor(s), etc.) are formed using the semiconductor mesa(s) and, optionally, additional device(s) (e.g., polysilicon resistor(s)) can be formed within the trenches between adjacent semiconductor mesas. Subsequently, middle of the line (MOL) dielectrics (e.g., a conformal etch stop layer and a blanket interlayer dielectric (ILD) layer) are deposited over the device(s), thereby filling any remaining space within the trenches and completing the STI regions. Also disclosed is an IC structure formed using the method.

公开(公告)号：US20180323066A1

公开(公告)日：2018-11-08

申请号：US15584121

申请日：2017-05-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Michel J. Abou-Khalil ,  Steven M. Shank ,  Alvin J. Joseph ,  Michael J. Zierak

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/16 ,  H01L29/04 ,  H01L29/10 ,  H01L21/762 ,  H01L21/306

CPC classification number: H01L21/02667 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/30604 ,  H01L21/76224 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/1095 ,  H01L29/16

Abstract: Device structures for a field-effect transistor and methods of forming a device structure for a field-effect transistor. A trench isolation region is formed in a substrate, and surrounds a semiconductor body. An undercut cavity region is also formed in the substrate. The undercut cavity region extends laterally beneath the semiconductor body and defines a body pedestal as a section of the substrate that is arranged in vertical alignment with the semiconductor body.

公开(公告)号：US10079248B2

公开(公告)日：2018-09-18

申请号：US15355231

申请日：2016-11-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Mark D. Jaffe ,  John J. Pekarik

IPC: H01L29/78 ,  H01L21/02 ,  H01L27/12 ,  H01L29/06 ,  H01L23/528 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/768 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L27/1203 ,  H01L21/265 ,  H01L21/743 ,  H01L21/76224 ,  H01L21/76838 ,  H01L21/823481 ,  H01L21/84 ,  H01L23/5283 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/0649 ,  H01L29/66477 ,  H01L29/66772 ,  H01L29/78615 ,  H01L29/78654

Abstract: Device structures for a field-effect transistor with a body contact and methods of forming such device structures. An opening is formed that extends through a device layer of a silicon-on-insulator (SOI) substrate and into a buried oxide layer of the silicon-on-insulator substrate. The buried oxide layer is laterally etched at the location of the opening to define a cavity in the buried oxide layer. The cavity is located partially beneath a section of the device layer, and the cavity is filled with a semiconductor material to form a body contact. A well is formed in the section of the device layer, and the body contact is coupled with a portion of the well.

公开(公告)号：US09922973B1

公开(公告)日：2018-03-20

申请号：US15611184

申请日：2017-06-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  John J. Ellis-Monaghan ,  Thai Doan

IPC: H01L21/76 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L27/02 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/761 ,  H01L21/764 ,  H01L21/02 ,  H01L21/763

CPC classification number: H01L27/088 ,  H01L21/761 ,  H01L21/763 ,  H01L21/764 ,  H01L21/823481 ,  H01L21/823493 ,  H01L29/0603 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1079 ,  H01L29/1095

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to switches with deep trench depletion and isolation structures and methods of manufacture. The structure includes a bulk substrate with a fully depleted region below source and drain regions of at least one gate stack and confined by deep trench isolation structures lined with doped material.