公开(公告)号：US09391164B2

公开(公告)日：2016-07-12

申请号：US14699843

申请日：2015-04-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Kisik Choi ,  Vijay Narayanan

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/28 ,  H01L21/324 ,  H01L29/423 ,  H01L21/321

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/28017 ,  H01L21/28088 ,  H01L21/32055 ,  H01L21/321 ,  H01L21/324 ,  H01L29/4232 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/6681

Abstract: A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.

公开(公告)号：US20160163814A1

公开(公告)日：2016-06-09

申请号：US14563009

申请日：2014-12-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Takashi Ando ,  Balaji Kannan ,  Vijay Narayanan

IPC: H01L29/49 ,  H01L21/28

CPC classification number: H01L21/823828 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/66871

Abstract: A method of forming a transistor device includes forming an interfacial layer and a dielectric layer over a substrate; and forming a workfunction metal layer over the dielectric layer, the workfunction metal layer comprising a titanium-aluminum-carbon-oxygen (TiAlCO) layer.

Abstract translation: 形成晶体管器件的方法包括在衬底上形成界面层和电介质层; 以及在所述电介质层上形成功函数金属层，所述功函数金属层包含钛 - 铝 - 碳 - 氧（TiAlCO）层。

公开(公告)号：US20150249015A1

公开(公告)日：2015-09-03

申请号：US14707822

申请日：2015-05-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Kisik Choi ,  Wing L. Lai ,  Vijay Narayanan ,  Ravikumar Ramachandran

IPC: H01L21/28

CPC classification number: H01L21/28229 ,  H01L21/28185 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/495 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/7851

Abstract: A method for semiconductor fabrication includes forming at least one of a diffusion barrier layer and a metal containing layer over a dielectric layer in a gate cavity. A first anneal is performed to diffuse elements from the at least one of the diffusion barrier layer and the metal containing layer into the dielectric layer. The metal containing layer and the diffusion barrier layer are removed. A second anneal is performed to adjust diffusion of the elements in the dielectric layer to provide a gate dielectric region.

公开(公告)号：US20150228749A1

公开(公告)日：2015-08-13

申请号：US14696015

申请日：2015-04-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Kisik Choi ,  Wing L. Lai ,  Vijay Narayanan ,  Ravikumar Ramachandran

IPC: H01L29/51 ,  H01L29/49 ,  H01L29/06 ,  H01L29/78 ,  H01L27/092 ,  H01L29/423

CPC classification number: H01L21/28229 ,  H01L21/28185 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/495 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/7851

Abstract: A method for semiconductor fabrication includes forming at least one of a diffusion barrier layer and a metal containing layer over a dielectric layer in a gate cavity. A first anneal is performed to diffuse elements from the at least one of the diffusion barrier layer and the metal containing layer into the dielectric layer. The metal containing layer and the diffusion barrier layer are removed. A second anneal is performed to adjust diffusion of the elements in the dielectric layer to provide a gate dielectric region.

公开(公告)号：US20150035073A1

公开(公告)日：2015-02-05

申请号：US13959375

申请日：2013-08-05

Applicant: GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Kisik Choi ,  Wing L. Lai ,  Vijay Narayanan ,  Ravikumar Ramachandran

IPC: H01L21/28 ,  H01L27/092

CPC classification number: H01L21/28229 ,  H01L21/28185 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/495 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/7851

Abstract: A method for semiconductor fabrication includes forming at least one of a diffusion barrier layer and a metal containing layer over a dielectric layer in a gate cavity. A first anneal is performed to diffuse elements from the at least one of the diffusion barrier layer and the metal containing layer into the dielectric layer. The metal containing layer and the diffusion barrier layer are removed. A second anneal is performed to adjust diffusion of the elements in the dielectric layer to provide a gate dielectric region.

Abstract translation: 一种用于半导体制造的方法包括在栅腔中的介电层上形成扩散阻挡层和含金属层中的至少一个。 执行第一退火以将元件从扩散阻挡层和含金属层中的至少一个扩散到电介质层中。 去除含金属层和扩散阻挡层。 执行第二次退火以调节介电层中的元件的扩散以提供栅极电介质区域。

公开(公告)号：US20180331040A1

公开(公告)日：2018-11-15

申请号：US16040752

申请日：2018-07-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

Inventor： Takashi Ando ,  Hiroaki Niimi ,  Tenko Yamashita

IPC: H01L23/535 ,  H01L21/768 ,  H01L21/02 ,  H01L29/51 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L23/535 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02192 ,  H01L21/285 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76846 ,  H01L21/76877 ,  H01L21/823871 ,  H01L23/485 ,  H01L27/092 ,  H01L29/517 ,  H01L29/66545

Abstract: A method of making a semiconductor device includes forming a first source/drain trench and a second source/drain trench over a first and second source/drain region, respectively; forming a first silicon dioxide layer in the first source/drain trench and a second silicon dioxide layer in the second source/drain trench; forming a first source/drain contact over the first source/drain region, the first source/drain contact including a first tri-layer contact disposed between the first silicon dioxide layer and a first conductive material; and forming a second source/drain contact over the second source/drain region, the second source/drain contact including a second tri-layer contact disposed between the second silicon dioxide layer and a second conductive material; wherein the first tri-layer contact includes a first metal oxide layer in contact with the first silicon dioxide layer, and the second tri-layer contact includes a second metal oxide layer in contact with the second silicon dioxide layer.

公开(公告)号：US09972697B2

公开(公告)日：2018-05-15

申请号：US15267887

申请日：2016-09-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Kisik Choi ,  Vijay Narayanan

IPC: H01L21/3205 ,  H01L29/66 ,  H01L21/28 ,  H01L21/324 ,  H01L29/423 ,  H01L21/321 ,  H01L21/02

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/28017 ,  H01L21/28088 ,  H01L21/32055 ,  H01L21/321 ,  H01L21/324 ,  H01L29/4232 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/6681

Abstract: A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.

公开(公告)号：US09691662B2

公开(公告)日：2017-06-27

申请号：US15338894

申请日：2016-10-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Takashi Ando ,  Min Dai ,  Balaji Kannan ,  Siddarth A. Krishnan ,  Unoh Kwon

IPC: H01L21/8234 ,  H01L29/49 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/324 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L21/823412 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/785

Abstract: Selective deposition of a silicon-germanium surface layer on semiconductor surfaces can be employed to provide two types of channel regions for field effect transistors. Anneal of an adjustment oxide material on a stack of a silicon-based gate dielectric and a high dielectric constant (high-k) gate dielectric can be employed to form an interfacial adjustment oxide layer contacting a subset of channel regions. Oxygen deficiency can be induced in portions of the high-k dielectric layer overlying the interfacial adjustment oxide layer by deposition of a first work function metallic material layer and a capping layer and a subsequent anneal. Oxygen deficiency can be selectively removed by physically exposing portions of the high-k dielectric layer. A second work function metallic material layer and a gate conductor layer can be deposited and planarized to form gate electrodes that provide multiple effective work functions.

公开(公告)号：US20160351453A1

公开(公告)日：2016-12-01

申请号：US14721402

申请日：2015-05-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Takashi Ando ,  Aritra Dasgupta ,  Balaji Kannan ,  Unoh Kwon

IPC: H01L21/8238 ,  H01L29/49 ,  H01L29/423 ,  H01L21/324 ,  H01L27/092

CPC classification number: H01L21/823857 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/324 ,  H01L21/823842 ,  H01L27/0922 ,  H01L29/105 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: Embodiments of the present invention provide a process that maintains a “keep cap” metal nitride layer on PFET devices within a CMOS structure. The keep cap metal nitride layer is in place while an N-type work function metal is formed on the NFET devices within the CMOS structure. A sacrificial rare earth oxide layer, such as a lanthanum oxide layer is used to facilitate removal of the n-type work function metal selective to the keep cap metal nitride layer.

Abstract translation: 本发明的实施例提供了在CMOS结构内在PFET器件上保持“保持帽”金属氮化物层的工艺。 在CMOS结构内的NFET器件上形成N型功函数金属时，保持帽金属氮化物层就位。 使用诸如氧化镧层的牺牲稀土氧化物层来去除对保持帽金属氮化物层有选择性的n型功函数金属。

公开(公告)号：US09484427B2

公开(公告)日：2016-11-01

申请号：US14320831

申请日：2014-07-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Takashi Ando ,  Min Dai ,  Balaji Kannan ,  Siddarth A. Krishnan ,  Unoh Kwon

IPC: H01L29/49 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L21/823412 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/785

Abstract: Selective deposition of a silicon-germanium surface layer on semiconductor surfaces can be employed to provide two types of channel regions for field effect transistors. Anneal of an adjustment oxide material on a stack of a silicon-based gate dielectric and a high dielectric constant (high-k) gate dielectric can be employed to form an interfacial adjustment oxide layer contacting a subset of channel regions. Oxygen deficiency can be induced in portions of the high-k dielectric layer overlying the interfacial adjustment oxide layer by deposition of a first work function metallic material layer and a capping layer and a subsequent anneal. Oxygen deficiency can be selectively removed by physically exposing portions of the high-k dielectric layer. A second work function metallic material layer and a gate conductor layer can be deposited and planarized to form gate electrodes that provide multiple effective work functions.

Abstract translation: 硅 - 锗表面层在半导体表面上的选择性沉积可用于为场效应晶体管提供两种类型的沟道区。 在硅基栅极电介质和高介电常数（高k）栅极电介质的堆叠上的调整氧化物材料的退火可以用于形成接触通道区域子集的界面调整氧化物层。 通过沉积第一功函数金属材料层和封盖层和随后的退火，可以在覆盖界面调整氧化物层的高k电介质层的部分中诱导氧缺乏。 可以通过物理暴露高k电介质层的部分来选择性地去除氧缺乏。 可以将第二功函数金属材料层和栅极导体层沉积并平坦化以形成提供多个有效功函数的栅电极。