Abstract:
Embodiments of the present invention provide a process that maintains a “keep cap” metal nitride layer on PFET devices within a CMOS structure. The keep cap metal nitride layer is in place while an N-type work function metal is formed on the NFET devices within the CMOS structure. A sacrificial rare earth oxide layer, such as a lanthanum oxide layer is used to facilitate removal of the n-type work function metal selective to the keep cap metal nitride layer.
Abstract:
Methods of forming a metal resistor are provided. The methods may include: depositing a metal layer, e.g., tungsten, on a substrate; and forming the metal resistor by implanting a semiconductor species, e.g., silicon and/or germanium, into the metal layer to form a semiconductor-metal alloy layer from at least a portion of the metal layer. In certain embodiments, an adhesion layer may be deposited by ALD prior to metal layer depositing. The metal resistor has a sheet resistance that remains substantially constant prior to and after subsequent annealing.
Abstract:
Methods of forming a metal resistor are provided. The methods may include: depositing a metal layer, e.g., tungsten, on a substrate; and forming the metal resistor by implanting a semiconductor species, e.g., silicon and/or germanium, into the metal layer to form a semiconductor-metal alloy layer from at least a portion of the metal layer. In certain embodiments, an adhesion layer may be deposited by ALD prior to metal layer depositing. The metal resistor has a sheet resistance that remains substantially constant prior to and after subsequent annealing.
Abstract:
The disclosure relates to semiconductor structures and, more particularly, to structures with thinned dielectric material and methods of manufacture. The method includes depositing a high-k dielectric on a substrate. The method further includes depositing a titanium nitride film directly on the high-k while simultaneously etching the high-k dielectric.
Abstract:
Embodiments of the present invention provide a process that maintains a “keep cap” metal nitride layer on PFET devices within a CMOS structure. The keep cap metal nitride layer is in place while an N-type work function metal is formed on the NFET devices within the CMOS structure. A sacrificial rare earth oxide layer, such as a lanthanum oxide layer is used to facilitate removal of the n-type work function metal selective to the keep cap metal nitride layer.
Abstract:
One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include: forming a first work function metal over a set of fins having at least a first fin and a second fin; implanting the first work function metal with a first species; removing the implanted first work function metal from over the first fin such that a remaining portion of the implanted first work function metal remains over the second fin; forming a second work function metal over the set of fins including over the remaining portion of the implanted first work function metal; implanting the second work function metal with a second species; and forming a metal over the implanted second work function metal over the set of fins thereby forming the gate stack.
Abstract:
One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include: forming a first work function metal over a set of fins having at least a first fin and a second fin; implanting the first work function metal with a first species; removing the implanted first work function metal from over the first fin such that a remaining portion of the implanted first work function metal remains over the second fin; forming a second work function metal over the set of fins including over the remaining portion of the implanted first work function metal; implanting the second work function metal with a second species; and forming a metal over the implanted second work function metal over the set of fins thereby forming the gate stack.
Abstract:
A method of forming a finFET structure having an ion implanted intermediate region next to the channel region of a finFET gate. The intermediate region is formed in a manner to reduce or eliminate migration of the dopant to undoped regions of the finFET thus forming abrupt finFET junction.